文件名称:BCH_VLSI
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- 上传时间：2017-07-07
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文件大小：13.83mb
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使用HLS完成BCH编码的运算通路的设计，纯组合逻辑，对于65nm工艺可跑上1GHz。已经组合逻辑分为了多个部分，可在每一个部分之间插流水线。 附上可综合的纯RTL Code以及C++代码，以及Modelsim仿真。 可通过我的优化选项来学习如何优化HLS工具生产的代码。(BCH Encoder realized using HLS tool. Combinational logic.)
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下载文件列表
BCH_VLSI
BCH_VLSI\modelsim\work\_vmake
BCH_VLSI\modelsim\work\_temp\vlogmfy7nh
BCH_VLSI\modelsim\work\_temp\vlogkd9ms9
BCH_VLSI\modelsim\work\_temp\vlog87rzn3
BCH_VLSI\modelsim\work\_temp\vlog6zjg23
BCH_VLSI\modelsim\work\_temp\vlog6hkgw2
BCH_VLSI\modelsim\work\_temp\vlog3dggxw
BCH_VLSI\modelsim\work\_temp
BCH_VLSI\modelsim\work\_info
BCH_VLSI\modelsim\work\@cycle_encoder_tb\verilog.rw
BCH_VLSI\modelsim\work\@cycle_encoder_tb\verilog.asm
BCH_VLSI\modelsim\work\@cycle_encoder_tb\_primary.vhd
BCH_VLSI\modelsim\work\@cycle_encoder_tb\_primary.dbs
BCH_VLSI\modelsim\work\@cycle_encoder_tb\_primary.dat
BCH_VLSI\modelsim\work\@cycle_encoder_tb
BCH_VLSI\modelsim\work\@cycle_encoder_parts_wrapper\verilog.rw
BCH_VLSI\modelsim\work\@cycle_encoder_parts_wrapper\verilog.asm
BCH_VLSI\modelsim\work\@cycle_encoder_parts_wrapper\_primary.vhd
BCH_VLSI\modelsim\work\@cycle_encoder_parts_wrapper\_primary.dbs
BCH_VLSI\modelsim\work\@cycle_encoder_parts_wrapper\_primary.dat
BCH_VLSI\modelsim\work\@cycle_encoder_parts_wrapper
BCH_VLSI\modelsim\work\@cycle_encoder_part_3\verilog.rw
BCH_VLSI\modelsim\work\@cycle_encoder_part_3\verilog.asm
BCH_VLSI\modelsim\work\@cycle_encoder_part_3\_primary.vhd
BCH_VLSI\modelsim\work\@cycle_encoder_part_3\_primary.dbs
BCH_VLSI\modelsim\work\@cycle_encoder_part_3\_primary.dat
BCH_VLSI\modelsim\work\@cycle_encoder_part_3
BCH_VLSI\modelsim\work\@cycle_encoder_part_2_2\verilog.rw
BCH_VLSI\modelsim\work\@cycle_encoder_part_2_2\verilog.asm
BCH_VLSI\modelsim\work\@cycle_encoder_part_2_2\_primary.vhd
BCH_VLSI\modelsim\work\@cycle_encoder_part_2_2\_primary.dbs
BCH_VLSI\modelsim\work\@cycle_encoder_part_2_2\_primary.dat
BCH_VLSI\modelsim\work\@cycle_encoder_part_2_2
BCH_VLSI\modelsim\work\@cycle_encoder_part_2_1\verilog.rw
BCH_VLSI\modelsim\work\@cycle_encoder_part_2_1\verilog.asm
BCH_VLSI\modelsim\work\@cycle_encoder_part_2_1\_primary.vhd
BCH_VLSI\modelsim\work\@cycle_encoder_part_2_1\_primary.dbs
BCH_VLSI\modelsim\work\@cycle_encoder_part_2_1\_primary.dat
BCH_VLSI\modelsim\work\@cycle_encoder_part_2_1
BCH_VLSI\modelsim\work\@cycle_encoder_part_1\verilog.rw
BCH_VLSI\modelsim\work\@cycle_encoder_part_1\verilog.asm
BCH_VLSI\modelsim\work\@cycle_encoder_part_1\_primary.vhd
BCH_VLSI\modelsim\work\@cycle_encoder_part_1\_primary.dbs
BCH_VLSI\modelsim\work\@cycle_encoder_part_1\_primary.dat
BCH_VLSI\modelsim\work\@cycle_encoder_part_1
BCH_VLSI\modelsim\work\@cycle_encoder\verilog.rw
BCH_VLSI\modelsim\work\@cycle_encoder\verilog.asm
BCH_VLSI\modelsim\work\@cycle_encoder\_primary.vhd
BCH_VLSI\modelsim\work\@cycle_encoder\_primary.dbs
BCH_VLSI\modelsim\work\@cycle_encoder\_primary.dat
BCH_VLSI\modelsim\work\@cycle_encoder
BCH_VLSI\modelsim\work
BCH_VLSI\modelsim\vsim.wlf
BCH_VLSI\modelsim\transcript
BCH_VLSI\modelsim\modelsim.ini
BCH_VLSI\modelsim\Cycle_encoder_tb.sv
BCH_VLSI\modelsim\Cycle_encoder_parts_wrapper.v
BCH_VLSI\modelsim\Cycle_encoder_part_3.v
BCH_VLSI\modelsim\Cycle_encoder_part_2_2.v
BCH_VLSI\modelsim\Cycle_encoder_part_2_1.v
BCH_VLSI\modelsim\Cycle_encoder_part_1.v
BCH_VLSI\modelsim\Cycle_encoder.v
BCH_VLSI\modelsim\Cycle_encoder.mpf
BCH_VLSI\modelsim\Cycle_encoder.cr.mti
BCH_VLSI\modelsim
BCH_VLSI\RTL_viewer\parts_description.txt
BCH_VLSI\RTL_viewer\parts.qws
BCH_VLSI\RTL_viewer\parts.qsf
BCH_VLSI\C++
BCH_VLSI\C++\BCH_VLSI
BCH_VLSI\C++\BCH_VLSI\BCH_VLSI.cpp
BCH_VLSI\C++\BCH_VLSI\BCH_VLSI.h
BCH_VLSI\C++\BCH_VLSI\BCH_VLSI.v11.suo
BCH_VLSI\C++\BCH_VLSI\BCH_VLSI.vcxproj
BCH_VLSI\C++\BCH_VLSI\BCH_VLSI.vcxproj.filters
BCH_VLSI\C++\BCH_VLSI\Debug
BCH_VLSI\C++\BCH_VLSI\Debug\BCH_VLSI.lastbuildstate
BCH_VLSI\C++\BCH_VLSI\Debug\BCH_VLSI.log
BCH_VLSI\C++\BCH_VLSI\Debug\BCH_VLSI.obj
BCH_VLSI\C++\BCH_VLSI\Debug\CL.read.1.tlog
BCH_VLSI\C++\BCH_VLSI\Debug\CL.write.1.tlog
BCH_VLSI\C++\BCH_VLSI\Debug\link-cvtres.read.1.tlog
BCH_VLSI\C++\BCH_VLSI\Debug\link-cvtres.write.1.tlog
BCH_VLSI\C++\BCH_VLSI\Debug\link-rc.read.1.tlog
BCH_VLSI\C++\BCH_VLSI\Debug\link-rc.write.1.tlog
BCH_VLSI\C++\BCH_VLSI\Debug\link.3172-cvtres.read.1.tlog
BCH_VLSI\C++\BCH_VLSI\Debug\link.3172-cvtres.write.1.tlog
BCH_VLSI\C++\BCH_VLSI\Debug\link.3172-rc.read.1.tlog
BCH_VLSI\C++\BCH_VLSI\Debug\link.3172-rc.write.1.tlog
BCH_VLSI\C++\BCH_VLSI\Debug\link.3172.read.1.tlog
BCH_VLSI\C++\BCH_VLSI\Debug\link.3172.write.1.tlog
BCH_VLSI\C++\BCH_VLSI\Debug\link.3600-cvtres.read.1.tlog
BCH_VLSI\C++\BCH_VLSI\Debug\link.3600-cvtres.write.1.tlog
BCH_VLSI\C++\BCH_VLSI\Debug\link.3600-rc.read.1.tlog
BCH_VLSI\C++\BCH_VLSI\Debug\link.3600-rc.write.1.tlog
BCH_VLSI\C++\BCH_VLSI\Debug\link.3600.read.1.tlog
BCH_VLSI\C++\BCH_VLSI\Debug\link.3600.write.1.tlog
BCH_VLSI\C++\BCH_VLSI\Debug\link.3760-cvtres.read.1.tlog
BCH_VLSI\C++\BCH_VLSI\Debug\link.3760-cvtres.write.1.tlog
BCH_VLSI\modelsim\work\_vmake
BCH_VLSI\modelsim\work\_temp\vlogmfy7nh
BCH_VLSI\modelsim\work\_temp\vlogkd9ms9
BCH_VLSI\modelsim\work\_temp\vlog87rzn3
BCH_VLSI\modelsim\work\_temp\vlog6zjg23
BCH_VLSI\modelsim\work\_temp\vlog6hkgw2
BCH_VLSI\modelsim\work\_temp\vlog3dggxw
BCH_VLSI\modelsim\work\_temp
BCH_VLSI\modelsim\work\_info
BCH_VLSI\modelsim\work\@cycle_encoder_tb\verilog.rw
BCH_VLSI\modelsim\work\@cycle_encoder_tb\verilog.asm
BCH_VLSI\modelsim\work\@cycle_encoder_tb\_primary.vhd
BCH_VLSI\modelsim\work\@cycle_encoder_tb\_primary.dbs
BCH_VLSI\modelsim\work\@cycle_encoder_tb\_primary.dat
BCH_VLSI\modelsim\work\@cycle_encoder_tb
BCH_VLSI\modelsim\work\@cycle_encoder_parts_wrapper\verilog.rw
BCH_VLSI\modelsim\work\@cycle_encoder_parts_wrapper\verilog.asm
BCH_VLSI\modelsim\work\@cycle_encoder_parts_wrapper\_primary.vhd
BCH_VLSI\modelsim\work\@cycle_encoder_parts_wrapper\_primary.dbs
BCH_VLSI\modelsim\work\@cycle_encoder_parts_wrapper\_primary.dat
BCH_VLSI\modelsim\work\@cycle_encoder_parts_wrapper
BCH_VLSI\modelsim\work\@cycle_encoder_part_3\verilog.rw
BCH_VLSI\modelsim\work\@cycle_encoder_part_3\verilog.asm
BCH_VLSI\modelsim\work\@cycle_encoder_part_3\_primary.vhd
BCH_VLSI\modelsim\work\@cycle_encoder_part_3\_primary.dbs
BCH_VLSI\modelsim\work\@cycle_encoder_part_3\_primary.dat
BCH_VLSI\modelsim\work\@cycle_encoder_part_3
BCH_VLSI\modelsim\work\@cycle_encoder_part_2_2\verilog.rw
BCH_VLSI\modelsim\work\@cycle_encoder_part_2_2\verilog.asm
BCH_VLSI\modelsim\work\@cycle_encoder_part_2_2\_primary.vhd
BCH_VLSI\modelsim\work\@cycle_encoder_part_2_2\_primary.dbs
BCH_VLSI\modelsim\work\@cycle_encoder_part_2_2\_primary.dat
BCH_VLSI\modelsim\work\@cycle_encoder_part_2_2
BCH_VLSI\modelsim\work\@cycle_encoder_part_2_1\verilog.rw
BCH_VLSI\modelsim\work\@cycle_encoder_part_2_1\verilog.asm
BCH_VLSI\modelsim\work\@cycle_encoder_part_2_1\_primary.vhd
BCH_VLSI\modelsim\work\@cycle_encoder_part_2_1\_primary.dbs
BCH_VLSI\modelsim\work\@cycle_encoder_part_2_1\_primary.dat
BCH_VLSI\modelsim\work\@cycle_encoder_part_2_1
BCH_VLSI\modelsim\work\@cycle_encoder_part_1\verilog.rw
BCH_VLSI\modelsim\work\@cycle_encoder_part_1\verilog.asm
BCH_VLSI\modelsim\work\@cycle_encoder_part_1\_primary.vhd
BCH_VLSI\modelsim\work\@cycle_encoder_part_1\_primary.dbs
BCH_VLSI\modelsim\work\@cycle_encoder_part_1\_primary.dat
BCH_VLSI\modelsim\work\@cycle_encoder_part_1
BCH_VLSI\modelsim\work\@cycle_encoder\verilog.rw
BCH_VLSI\modelsim\work\@cycle_encoder\verilog.asm
BCH_VLSI\modelsim\work\@cycle_encoder\_primary.vhd
BCH_VLSI\modelsim\work\@cycle_encoder\_primary.dbs
BCH_VLSI\modelsim\work\@cycle_encoder\_primary.dat
BCH_VLSI\modelsim\work\@cycle_encoder
BCH_VLSI\modelsim\work
BCH_VLSI\modelsim\vsim.wlf
BCH_VLSI\modelsim\transcript
BCH_VLSI\modelsim\modelsim.ini
BCH_VLSI\modelsim\Cycle_encoder_tb.sv
BCH_VLSI\modelsim\Cycle_encoder_parts_wrapper.v
BCH_VLSI\modelsim\Cycle_encoder_part_3.v
BCH_VLSI\modelsim\Cycle_encoder_part_2_2.v
BCH_VLSI\modelsim\Cycle_encoder_part_2_1.v
BCH_VLSI\modelsim\Cycle_encoder_part_1.v
BCH_VLSI\modelsim\Cycle_encoder.v
BCH_VLSI\modelsim\Cycle_encoder.mpf
BCH_VLSI\modelsim\Cycle_encoder.cr.mti
BCH_VLSI\modelsim
BCH_VLSI\RTL_viewer\parts_description.txt
BCH_VLSI\RTL_viewer\parts.qws
BCH_VLSI\RTL_viewer\parts.qsf
BCH_VLSI\C++
BCH_VLSI\C++\BCH_VLSI
BCH_VLSI\C++\BCH_VLSI\BCH_VLSI.cpp
BCH_VLSI\C++\BCH_VLSI\BCH_VLSI.h
BCH_VLSI\C++\BCH_VLSI\BCH_VLSI.v11.suo
BCH_VLSI\C++\BCH_VLSI\BCH_VLSI.vcxproj
BCH_VLSI\C++\BCH_VLSI\BCH_VLSI.vcxproj.filters
BCH_VLSI\C++\BCH_VLSI\Debug
BCH_VLSI\C++\BCH_VLSI\Debug\BCH_VLSI.lastbuildstate
BCH_VLSI\C++\BCH_VLSI\Debug\BCH_VLSI.log
BCH_VLSI\C++\BCH_VLSI\Debug\BCH_VLSI.obj
BCH_VLSI\C++\BCH_VLSI\Debug\CL.read.1.tlog
BCH_VLSI\C++\BCH_VLSI\Debug\CL.write.1.tlog
BCH_VLSI\C++\BCH_VLSI\Debug\link-cvtres.read.1.tlog
BCH_VLSI\C++\BCH_VLSI\Debug\link-cvtres.write.1.tlog
BCH_VLSI\C++\BCH_VLSI\Debug\link-rc.read.1.tlog
BCH_VLSI\C++\BCH_VLSI\Debug\link-rc.write.1.tlog
BCH_VLSI\C++\BCH_VLSI\Debug\link.3172-cvtres.read.1.tlog
BCH_VLSI\C++\BCH_VLSI\Debug\link.3172-cvtres.write.1.tlog
BCH_VLSI\C++\BCH_VLSI\Debug\link.3172-rc.read.1.tlog
BCH_VLSI\C++\BCH_VLSI\Debug\link.3172-rc.write.1.tlog
BCH_VLSI\C++\BCH_VLSI\Debug\link.3172.read.1.tlog
BCH_VLSI\C++\BCH_VLSI\Debug\link.3172.write.1.tlog
BCH_VLSI\C++\BCH_VLSI\Debug\link.3600-cvtres.read.1.tlog
BCH_VLSI\C++\BCH_VLSI\Debug\link.3600-cvtres.write.1.tlog
BCH_VLSI\C++\BCH_VLSI\Debug\link.3600-rc.read.1.tlog
BCH_VLSI\C++\BCH_VLSI\Debug\link.3600-rc.write.1.tlog
BCH_VLSI\C++\BCH_VLSI\Debug\link.3600.read.1.tlog
BCH_VLSI\C++\BCH_VLSI\Debug\link.3600.write.1.tlog
BCH_VLSI\C++\BCH_VLSI\Debug\link.3760-cvtres.read.1.tlog
BCH_VLSI\C++\BCH_VLSI\Debug\link.3760-cvtres.write.1.tlog
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