文件名称:F0501
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- 上传时间:2017-07-12
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文件大小:7.32mb
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已下载:1次
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汽车VCU控制器测试工装的程序,STM32单片机扩展总线读写FPGA内部RAM,DDS方式产生PWM,PWM频率,脉宽测量功能(Automotive VCU controller test tooling procedures, STM32 microcontroller expansion bus read and write FPGA, the internal RAM, DDS way to generate PWM, PWM frequency, pulse width measurement function)
(系统自动生成,下载前可以参看下载内容)
下载文件列表
F0501\CODE\CLK_DCM.v
F0501\CODE\CLK_DIVN.v
F0501\CODE\DPRAM_Control.v
F0501\CODE\fuse.log
F0501\CODE\fuse.xmsgs
F0501\CODE\fuseRelaunch.cmd
F0501\CODE\ipcore_dir\Adder_10bit\doc\c_addsub_v11_0_readme.txt
F0501\CODE\ipcore_dir\Adder_10bit\doc\c_addsub_v11_0_vinfo.html
F0501\CODE\ipcore_dir\Adder_10bit\doc\ds214_addsub.pdf
F0501\CODE\ipcore_dir\Adder_10bit.asy
F0501\CODE\ipcore_dir\Adder_10bit.gise
F0501\CODE\ipcore_dir\Adder_10bit.ncf
F0501\CODE\ipcore_dir\Adder_10bit.ngc
F0501\CODE\ipcore_dir\Adder_10bit.sym
F0501\CODE\ipcore_dir\Adder_10bit.v
F0501\CODE\ipcore_dir\Adder_10bit.veo
F0501\CODE\ipcore_dir\Adder_10bit.xco
F0501\CODE\ipcore_dir\Adder_10bit.xise
F0501\CODE\ipcore_dir\Adder_10bit_flist.txt
F0501\CODE\ipcore_dir\Adder_10bit_xmdf.tcl
F0501\CODE\ipcore_dir\Adder_32bit\doc\c_addsub_v11_0_readme.txt
F0501\CODE\ipcore_dir\Adder_32bit\doc\c_addsub_v11_0_vinfo.html
F0501\CODE\ipcore_dir\Adder_32bit\doc\ds214_addsub.pdf
F0501\CODE\ipcore_dir\Adder_32bit.asy
F0501\CODE\ipcore_dir\Adder_32bit.gise
F0501\CODE\ipcore_dir\Adder_32bit.ncf
F0501\CODE\ipcore_dir\Adder_32bit.ngc
F0501\CODE\ipcore_dir\Adder_32bit.sym
F0501\CODE\ipcore_dir\Adder_32bit.v
F0501\CODE\ipcore_dir\Adder_32bit.veo
F0501\CODE\ipcore_dir\Adder_32bit.xco
F0501\CODE\ipcore_dir\Adder_32bit.xise
F0501\CODE\ipcore_dir\Adder_32bit_flist.txt
F0501\CODE\ipcore_dir\Adder_32bit_xmdf.tcl
F0501\CODE\ipcore_dir\coregen.cgp
F0501\CODE\ipcore_dir\coregen.log
F0501\CODE\ipcore_dir\core_resources.txt
F0501\CODE\ipcore_dir\Counter_10bit\doc\c_counter_binary_v11_0_readme.txt
F0501\CODE\ipcore_dir\Counter_10bit\doc\c_counter_binary_v11_0_vinfo.html
F0501\CODE\ipcore_dir\Counter_10bit\doc\ds215_counter.pdf
F0501\CODE\ipcore_dir\Counter_10bit.asy
F0501\CODE\ipcore_dir\Counter_10bit.gise
F0501\CODE\ipcore_dir\Counter_10bit.ncf
F0501\CODE\ipcore_dir\Counter_10bit.ngc
F0501\CODE\ipcore_dir\Counter_10bit.sym
F0501\CODE\ipcore_dir\Counter_10bit.v
F0501\CODE\ipcore_dir\Counter_10bit.veo
F0501\CODE\ipcore_dir\Counter_10bit.xco
F0501\CODE\ipcore_dir\Counter_10bit.xise
F0501\CODE\ipcore_dir\Counter_10bit_flist.txt
F0501\CODE\ipcore_dir\Counter_10bit_xmdf.tcl
F0501\CODE\ipcore_dir\Counter_32bit\doc\c_counter_binary_v11_0_readme.txt
F0501\CODE\ipcore_dir\Counter_32bit\doc\c_counter_binary_v11_0_vinfo.html
F0501\CODE\ipcore_dir\Counter_32bit\doc\ds215_counter.pdf
F0501\CODE\ipcore_dir\Counter_32bit.asy
F0501\CODE\ipcore_dir\Counter_32bit.gise
F0501\CODE\ipcore_dir\Counter_32bit.ncf
F0501\CODE\ipcore_dir\Counter_32bit.ngc
F0501\CODE\ipcore_dir\Counter_32bit.sym
F0501\CODE\ipcore_dir\Counter_32bit.v
F0501\CODE\ipcore_dir\Counter_32bit.veo
F0501\CODE\ipcore_dir\Counter_32bit.xco
F0501\CODE\ipcore_dir\Counter_32bit.xise
F0501\CODE\ipcore_dir\Counter_32bit_flist.txt
F0501\CODE\ipcore_dir\Counter_32bit_xmdf.tcl
F0501\CODE\ipcore_dir\create_Adder_10bit.tcl
F0501\CODE\ipcore_dir\create_Adder_32bit.tcl
F0501\CODE\ipcore_dir\create_Counter_10bit.tcl
F0501\CODE\ipcore_dir\create_Counter_32bit.tcl
F0501\CODE\ipcore_dir\create_DATA_RAM.tcl
F0501\CODE\ipcore_dir\create_eth.tcl
F0501\CODE\ipcore_dir\create_s.tcl
F0501\CODE\ipcore_dir\DATA_RAM\blk_mem_gen_v7_3_readme.txt
F0501\CODE\ipcore_dir\DATA_RAM\doc\blk_mem_gen_v7_3_vinfo.html
F0501\CODE\ipcore_dir\DATA_RAM\doc\pg058-blk-mem-gen.pdf
F0501\CODE\ipcore_dir\DATA_RAM\example_design\DATA_RAM_exdes.ucf
F0501\CODE\ipcore_dir\DATA_RAM\example_design\DATA_RAM_exdes.vhd
F0501\CODE\ipcore_dir\DATA_RAM\example_design\DATA_RAM_exdes.xdc
F0501\CODE\ipcore_dir\DATA_RAM\example_design\DATA_RAM_prod.vhd
F0501\CODE\ipcore_dir\DATA_RAM\implement\implement.bat
F0501\CODE\ipcore_dir\DATA_RAM\implement\implement.sh
F0501\CODE\ipcore_dir\DATA_RAM\implement\planAhead_ise.bat
F0501\CODE\ipcore_dir\DATA_RAM\implement\planAhead_ise.sh
F0501\CODE\ipcore_dir\DATA_RAM\implement\planAhead_ise.tcl
F0501\CODE\ipcore_dir\DATA_RAM\implement\xst.prj
F0501\CODE\ipcore_dir\DATA_RAM\implement\xst.scr
F0501\CODE\ipcore_dir\DATA_RAM\simulation\addr_gen.vhd
F0501\CODE\ipcore_dir\DATA_RAM\simulation\bmg_stim_gen.vhd
F0501\CODE\ipcore_dir\DATA_RAM\simulation\bmg_tb_pkg.vhd
F0501\CODE\ipcore_dir\DATA_RAM\simulation\checker.vhd
F0501\CODE\ipcore_dir\DATA_RAM\simulation\data_gen.vhd
F0501\CODE\ipcore_dir\DATA_RAM\simulation\DATA_RAM_synth.vhd
F0501\CODE\ipcore_dir\DATA_RAM\simulation\DATA_RAM_tb.vhd
F0501\CODE\ipcore_dir\DATA_RAM\simulation\functional\simcmds.tcl
F0501\CODE\ipcore_dir\DATA_RAM\simulation\functional\simulate_isim.bat
F0501\CODE\ipcore_dir\DATA_RAM\simulation\functional\simulate_mti.bat
F0501\CODE\ipcore_dir\DATA_RAM\simulation\functional\simulate_mti.do
F0501\CODE\ipcore_dir\DATA_RAM\simulation\functional\simulate_mti.sh
F0501\CODE\ipcore_dir\DATA_RAM\simulation\functional\simulate_ncsim.sh
F0501\CODE\ipcore_dir\DATA_RAM\simulation\functional\simulate_vcs.sh
F0501\CODE\CLK_DIVN.v
F0501\CODE\DPRAM_Control.v
F0501\CODE\fuse.log
F0501\CODE\fuse.xmsgs
F0501\CODE\fuseRelaunch.cmd
F0501\CODE\ipcore_dir\Adder_10bit\doc\c_addsub_v11_0_readme.txt
F0501\CODE\ipcore_dir\Adder_10bit\doc\c_addsub_v11_0_vinfo.html
F0501\CODE\ipcore_dir\Adder_10bit\doc\ds214_addsub.pdf
F0501\CODE\ipcore_dir\Adder_10bit.asy
F0501\CODE\ipcore_dir\Adder_10bit.gise
F0501\CODE\ipcore_dir\Adder_10bit.ncf
F0501\CODE\ipcore_dir\Adder_10bit.ngc
F0501\CODE\ipcore_dir\Adder_10bit.sym
F0501\CODE\ipcore_dir\Adder_10bit.v
F0501\CODE\ipcore_dir\Adder_10bit.veo
F0501\CODE\ipcore_dir\Adder_10bit.xco
F0501\CODE\ipcore_dir\Adder_10bit.xise
F0501\CODE\ipcore_dir\Adder_10bit_flist.txt
F0501\CODE\ipcore_dir\Adder_10bit_xmdf.tcl
F0501\CODE\ipcore_dir\Adder_32bit\doc\c_addsub_v11_0_readme.txt
F0501\CODE\ipcore_dir\Adder_32bit\doc\c_addsub_v11_0_vinfo.html
F0501\CODE\ipcore_dir\Adder_32bit\doc\ds214_addsub.pdf
F0501\CODE\ipcore_dir\Adder_32bit.asy
F0501\CODE\ipcore_dir\Adder_32bit.gise
F0501\CODE\ipcore_dir\Adder_32bit.ncf
F0501\CODE\ipcore_dir\Adder_32bit.ngc
F0501\CODE\ipcore_dir\Adder_32bit.sym
F0501\CODE\ipcore_dir\Adder_32bit.v
F0501\CODE\ipcore_dir\Adder_32bit.veo
F0501\CODE\ipcore_dir\Adder_32bit.xco
F0501\CODE\ipcore_dir\Adder_32bit.xise
F0501\CODE\ipcore_dir\Adder_32bit_flist.txt
F0501\CODE\ipcore_dir\Adder_32bit_xmdf.tcl
F0501\CODE\ipcore_dir\coregen.cgp
F0501\CODE\ipcore_dir\coregen.log
F0501\CODE\ipcore_dir\core_resources.txt
F0501\CODE\ipcore_dir\Counter_10bit\doc\c_counter_binary_v11_0_readme.txt
F0501\CODE\ipcore_dir\Counter_10bit\doc\c_counter_binary_v11_0_vinfo.html
F0501\CODE\ipcore_dir\Counter_10bit\doc\ds215_counter.pdf
F0501\CODE\ipcore_dir\Counter_10bit.asy
F0501\CODE\ipcore_dir\Counter_10bit.gise
F0501\CODE\ipcore_dir\Counter_10bit.ncf
F0501\CODE\ipcore_dir\Counter_10bit.ngc
F0501\CODE\ipcore_dir\Counter_10bit.sym
F0501\CODE\ipcore_dir\Counter_10bit.v
F0501\CODE\ipcore_dir\Counter_10bit.veo
F0501\CODE\ipcore_dir\Counter_10bit.xco
F0501\CODE\ipcore_dir\Counter_10bit.xise
F0501\CODE\ipcore_dir\Counter_10bit_flist.txt
F0501\CODE\ipcore_dir\Counter_10bit_xmdf.tcl
F0501\CODE\ipcore_dir\Counter_32bit\doc\c_counter_binary_v11_0_readme.txt
F0501\CODE\ipcore_dir\Counter_32bit\doc\c_counter_binary_v11_0_vinfo.html
F0501\CODE\ipcore_dir\Counter_32bit\doc\ds215_counter.pdf
F0501\CODE\ipcore_dir\Counter_32bit.asy
F0501\CODE\ipcore_dir\Counter_32bit.gise
F0501\CODE\ipcore_dir\Counter_32bit.ncf
F0501\CODE\ipcore_dir\Counter_32bit.ngc
F0501\CODE\ipcore_dir\Counter_32bit.sym
F0501\CODE\ipcore_dir\Counter_32bit.v
F0501\CODE\ipcore_dir\Counter_32bit.veo
F0501\CODE\ipcore_dir\Counter_32bit.xco
F0501\CODE\ipcore_dir\Counter_32bit.xise
F0501\CODE\ipcore_dir\Counter_32bit_flist.txt
F0501\CODE\ipcore_dir\Counter_32bit_xmdf.tcl
F0501\CODE\ipcore_dir\create_Adder_10bit.tcl
F0501\CODE\ipcore_dir\create_Adder_32bit.tcl
F0501\CODE\ipcore_dir\create_Counter_10bit.tcl
F0501\CODE\ipcore_dir\create_Counter_32bit.tcl
F0501\CODE\ipcore_dir\create_DATA_RAM.tcl
F0501\CODE\ipcore_dir\create_eth.tcl
F0501\CODE\ipcore_dir\create_s.tcl
F0501\CODE\ipcore_dir\DATA_RAM\blk_mem_gen_v7_3_readme.txt
F0501\CODE\ipcore_dir\DATA_RAM\doc\blk_mem_gen_v7_3_vinfo.html
F0501\CODE\ipcore_dir\DATA_RAM\doc\pg058-blk-mem-gen.pdf
F0501\CODE\ipcore_dir\DATA_RAM\example_design\DATA_RAM_exdes.ucf
F0501\CODE\ipcore_dir\DATA_RAM\example_design\DATA_RAM_exdes.vhd
F0501\CODE\ipcore_dir\DATA_RAM\example_design\DATA_RAM_exdes.xdc
F0501\CODE\ipcore_dir\DATA_RAM\example_design\DATA_RAM_prod.vhd
F0501\CODE\ipcore_dir\DATA_RAM\implement\implement.bat
F0501\CODE\ipcore_dir\DATA_RAM\implement\implement.sh
F0501\CODE\ipcore_dir\DATA_RAM\implement\planAhead_ise.bat
F0501\CODE\ipcore_dir\DATA_RAM\implement\planAhead_ise.sh
F0501\CODE\ipcore_dir\DATA_RAM\implement\planAhead_ise.tcl
F0501\CODE\ipcore_dir\DATA_RAM\implement\xst.prj
F0501\CODE\ipcore_dir\DATA_RAM\implement\xst.scr
F0501\CODE\ipcore_dir\DATA_RAM\simulation\addr_gen.vhd
F0501\CODE\ipcore_dir\DATA_RAM\simulation\bmg_stim_gen.vhd
F0501\CODE\ipcore_dir\DATA_RAM\simulation\bmg_tb_pkg.vhd
F0501\CODE\ipcore_dir\DATA_RAM\simulation\checker.vhd
F0501\CODE\ipcore_dir\DATA_RAM\simulation\data_gen.vhd
F0501\CODE\ipcore_dir\DATA_RAM\simulation\DATA_RAM_synth.vhd
F0501\CODE\ipcore_dir\DATA_RAM\simulation\DATA_RAM_tb.vhd
F0501\CODE\ipcore_dir\DATA_RAM\simulation\functional\simcmds.tcl
F0501\CODE\ipcore_dir\DATA_RAM\simulation\functional\simulate_isim.bat
F0501\CODE\ipcore_dir\DATA_RAM\simulation\functional\simulate_mti.bat
F0501\CODE\ipcore_dir\DATA_RAM\simulation\functional\simulate_mti.do
F0501\CODE\ipcore_dir\DATA_RAM\simulation\functional\simulate_mti.sh
F0501\CODE\ipcore_dir\DATA_RAM\simulation\functional\simulate_ncsim.sh
F0501\CODE\ipcore_dir\DATA_RAM\simulation\functional\simulate_vcs.sh
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