按键消抖
工程说明
在系统设计中，消除按键抖动的方法五花八门，无论是硬件电路和软件设计都十分成熟。在本项目中，我们将用Verilog语言给出具体实现过程，设计一个程序来检查键值，有效滤除按键抖动区间20 ms的毛刺脉冲。

案例补充说明
在本案例中，我们使用Verilog HDL语言对按键消抖进行了设计，在这个过程中，我们可以了解到不同触发器有不同的工作原理和约束条件，即便是简单的一个按键功能，也有不可忽视的抖动过滤程序，这些都是在以后的设计工作中需要注意的。(Keystroke dithering

Engineering descr iption

In system design, there are many ways to eliminate the key jitter, both hardware circuit and software design are very mature. In this project, we will use Verilog language to give a specific implementation process, design a program to check the key value, effectively filter the key jitter interval 20 ms burr pulse.

Case Supplement

In this case, we use Verilog HDL language to key debounce is designed, in this process, we can understand the different trigger principle and different constraints, even a simple button function, also has the noticeable jitter filtering process, these are the need to pay attention to the design in later work.)