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文件名称:spiVerilog-master

  • 所属分类：
    VHDL/FPGA/Verilog
  • 标签属性：
    [Linux] [SHELL] [源码]
  • 上传时间：
    2017-08-09
  • 文件大小：
    1.09mb
  • 已下载：
    0次
  • 提 供 者：
    d.per*****
  • 相关连接：
    无
  • 下载说明：
    别用迅雷下载，失败请重下，重下不扣分！
修正介绍说明

介绍说明－－下载内容来自于网络，使用问题请自行百度

spiVerilog A Verilog SPI module
相关搜索： vhdl spi verilog

(系统自动生成,下载前可以参看下载内容)

下载文件列表

spiVerilog-master
spiVerilog-master\designWrapperTest_behav.wcfg
spiVerilog-master\sha-256.cache
spiVerilog-master\sha-256.cache\wt
spiVerilog-master\sha-256.cache\wt\java_command_handlers.wdf
spiVerilog-master\sha-256.cache\wt\project.wpc
spiVerilog-master\sha-256.cache\wt\synthesis.wdf
spiVerilog-master\sha-256.cache\wt\synthesis_details.wdf
spiVerilog-master\sha-256.cache\wt\webtalk_pa.xml
spiVerilog-master\sha-256.cache\wt\xsim.wdf
spiVerilog-master\sha-256.hw
spiVerilog-master\sha-256.hw\sha-256.lpr
spiVerilog-master\sha-256.ip_user_files
spiVerilog-master\sha-256.ip_user_files\README.txt
spiVerilog-master\sha-256.runs
spiVerilog-master\sha-256.runs\.jobs
spiVerilog-master\sha-256.runs\.jobs\vrs_config_1.xml
spiVerilog-master\sha-256.runs\.jobs\vrs_config_10.xml
spiVerilog-master\sha-256.runs\.jobs\vrs_config_11.xml
spiVerilog-master\sha-256.runs\.jobs\vrs_config_12.xml
spiVerilog-master\sha-256.runs\.jobs\vrs_config_13.xml
spiVerilog-master\sha-256.runs\.jobs\vrs_config_14.xml
spiVerilog-master\sha-256.runs\.jobs\vrs_config_15.xml
spiVerilog-master\sha-256.runs\.jobs\vrs_config_16.xml
spiVerilog-master\sha-256.runs\.jobs\vrs_config_17.xml
spiVerilog-master\sha-256.runs\.jobs\vrs_config_18.xml
spiVerilog-master\sha-256.runs\.jobs\vrs_config_19.xml
spiVerilog-master\sha-256.runs\.jobs\vrs_config_2.xml
spiVerilog-master\sha-256.runs\.jobs\vrs_config_20.xml
spiVerilog-master\sha-256.runs\.jobs\vrs_config_21.xml
spiVerilog-master\sha-256.runs\.jobs\vrs_config_22.xml
spiVerilog-master\sha-256.runs\.jobs\vrs_config_3.xml
spiVerilog-master\sha-256.runs\.jobs\vrs_config_4.xml
spiVerilog-master\sha-256.runs\.jobs\vrs_config_5.xml
spiVerilog-master\sha-256.runs\.jobs\vrs_config_6.xml
spiVerilog-master\sha-256.runs\.jobs\vrs_config_7.xml
spiVerilog-master\sha-256.runs\.jobs\vrs_config_8.xml
spiVerilog-master\sha-256.runs\.jobs\vrs_config_9.xml
spiVerilog-master\sha-256.runs\impl_1
spiVerilog-master\sha-256.runs\impl_1\.Vivado_Implementation.queue.rst
spiVerilog-master\sha-256.runs\impl_1\.init_design.begin.rst
spiVerilog-master\sha-256.runs\impl_1\.init_design.end.rst
spiVerilog-master\sha-256.runs\impl_1\.opt_design.begin.rst
spiVerilog-master\sha-256.runs\impl_1\.opt_design.end.rst
spiVerilog-master\sha-256.runs\impl_1\.place_design.begin.rst
spiVerilog-master\sha-256.runs\impl_1\.place_design.end.rst
spiVerilog-master\sha-256.runs\impl_1\.route_design.begin.rst
spiVerilog-master\sha-256.runs\impl_1\.route_design.end.rst
spiVerilog-master\sha-256.runs\impl_1\.vivado.begin.rst
spiVerilog-master\sha-256.runs\impl_1\.vivado.end.rst
spiVerilog-master\sha-256.runs\impl_1\.write_bitstream.begin.rst
spiVerilog-master\sha-256.runs\impl_1\.write_bitstream.end.rst
spiVerilog-master\sha-256.runs\impl_1\ISEWrap.js
spiVerilog-master\sha-256.runs\impl_1\ISEWrap.sh
spiVerilog-master\sha-256.runs\impl_1\designWrapper.bit
spiVerilog-master\sha-256.runs\impl_1\designWrapper.tcl
spiVerilog-master\sha-256.runs\impl_1\designWrapper.vdi
spiVerilog-master\sha-256.runs\impl_1\designWrapper_clock_utilization_routed.rpt
spiVerilog-master\sha-256.runs\impl_1\designWrapper_control_sets_placed.rpt
spiVerilog-master\sha-256.runs\impl_1\designWrapper_drc_opted.rpt
spiVerilog-master\sha-256.runs\impl_1\designWrapper_drc_routed.pb
spiVerilog-master\sha-256.runs\impl_1\designWrapper_drc_routed.rpt
spiVerilog-master\sha-256.runs\impl_1\designWrapper_io_placed.rpt
spiVerilog-master\sha-256.runs\impl_1\designWrapper_opt.dcp
spiVerilog-master\sha-256.runs\impl_1\designWrapper_placed.dcp
spiVerilog-master\sha-256.runs\impl_1\designWrapper_power_routed.rpt
spiVerilog-master\sha-256.runs\impl_1\designWrapper_power_routed.rpx
spiVerilog-master\sha-256.runs\impl_1\designWrapper_power_summary_routed.pb
spiVerilog-master\sha-256.runs\impl_1\designWrapper_route_status.pb
spiVerilog-master\sha-256.runs\impl_1\designWrapper_route_status.rpt
spiVerilog-master\sha-256.runs\impl_1\designWrapper_routed.dcp
spiVerilog-master\sha-256.runs\impl_1\designWrapper_timing_summary_routed.rpt
spiVerilog-master\sha-256.runs\impl_1\designWrapper_timing_summary_routed.rpx
spiVerilog-master\sha-256.runs\impl_1\designWrapper_utilization_placed.pb
spiVerilog-master\sha-256.runs\impl_1\designWrapper_utilization_placed.rpt
spiVerilog-master\sha-256.runs\impl_1\gen_run.xml
spiVerilog-master\sha-256.runs\impl_1\htr.txt
spiVerilog-master\sha-256.runs\impl_1\init_design.pb
spiVerilog-master\sha-256.runs\impl_1\opt_design.pb
spiVerilog-master\sha-256.runs\impl_1\place_design.pb
spiVerilog-master\sha-256.runs\impl_1\project.wdf
spiVerilog-master\sha-256.runs\impl_1\route_design.pb
spiVerilog-master\sha-256.runs\impl_1\rundef.js
spiVerilog-master\sha-256.runs\impl_1\runme.bat
spiVerilog-master\sha-256.runs\impl_1\runme.log
spiVerilog-master\sha-256.runs\impl_1\runme.sh
spiVerilog-master\sha-256.runs\impl_1\vivado.jou
spiVerilog-master\sha-256.runs\impl_1\vivado.pb
spiVerilog-master\sha-256.runs\impl_1\write_bitstream.pb
spiVerilog-master\sha-256.runs\synth_1
spiVerilog-master\sha-256.runs\synth_1\.Vivado_Synthesis.queue.rst
spiVerilog-master\sha-256.runs\synth_1\.Xil
spiVerilog-master\sha-256.runs\synth_1\.Xil\designWrapper_propImpl.xdc
spiVerilog-master\sha-256.runs\synth_1\.vivado.begin.rst
spiVerilog-master\sha-256.runs\synth_1\.vivado.end.rst
spiVerilog-master\sha-256.runs\synth_1\ISEWrap.js
spiVerilog-master\sha-256.runs\synth_1\ISEWrap.sh
spiVerilog-master\sha-256.runs\synth_1\designWrapper.dcp
spiVerilog-master\sha-256.runs\synth_1\designWrapper.tcl
spiVerilog-master\sha-256.runs\synth_1\designWrapper.vds

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