文件名称:verify
介绍说明--下载内容来自于网络,使用问题请自行百度
一个复杂的uvm verification例子(a complicate uvm verification example)
相关搜索: uvm verify
(系统自动生成,下载前可以参看下载内容)
下载文件列表
verify\testcase\regcfg_tc.sv
verify\testcase\roic_base_tc.sv
verify\testcase\adc2spi_tc.sv
verify\testcase\rst_tc.sv
verify\testcase\i2c_dev_addr_tc.sv
verify\testcase\i2c_rd_err_tc.sv
verify\testcase\fifo_overflow_tc.sv
verify\tbench\top.v
verify\tbench\tbench.sv
verify\tbench\top_pad.v
verify\sim\regs_sim.csh
verify\sim\csrc\incr_filespace.db
verify\sim\csrc\Makefile
verify\sim\csrc\Makefile.hsopt
verify\sim\csrc\_vcsobj_archive_info_0.lst
verify\sim\csrc\rmapats.c
verify\sim\csrc\5NrIB_d.o
verify\sim\csrc\SIM_l.o
verify\sim\csrc\rmapats.h
verify\sim\csrc\rmapats_mop.o
verify\sim\csrc\vcspieces.incr
verify\sim\csrc\5NrI_d.o
verify\sim\csrc\_vcs_const_SIM_0.incr.dat
verify\sim\csrc\filelist.dpi
verify\sim\csrc\uvm_dpi.o
verify\sim\csrc\filelist
verify\sim\csrc\filelist.hsopt
verify\sim\csrc\filelist.hsopt.objs
verify\sim\csrc\checksum
verify\sim\csrc\_vcsobj_1_1.a.info
verify\sim\csrc\_vcsobj_1_1.a
verify\sim\csrc\rmapats.o
verify\sim\csrc\rmapats.m
verify\sim\csrc\product_timestamp
verify\sim\csrc\_vcs_etype_SIM_0.incr.dat
verify\sim\verdi.f
verify\sim\run.csh
verify\sim\ucli.key
verify\sim\novas_dump.log
verify\sim\regression.f
verify\sim\cm.log
verify\sim\debug.rc
verify\sim\code_all.f
verify\sim\coverage\urgReport\mod2.html
verify\sim\coverage\urgReport\mod15.html
verify\sim\coverage\urgReport\mod12.html
verify\sim\coverage\urgReport\mod13.html
verify\sim\coverage\urgReport\hierarchy.html
verify\sim\coverage\urgReport\mod7.html
verify\sim\coverage\urgReport\mod11.html
verify\sim\coverage\urgReport\mod21.html
verify\sim\coverage\urgReport\mod17.html
verify\sim\coverage\urgReport\session.xml
verify\sim\coverage\urgReport\mod1.html
verify\sim\coverage\urgReport\mod20.html
verify\sim\coverage\urgReport\modlist.html
verify\sim\coverage\urgReport\mod18.html
verify\sim\coverage\urgReport\tests.html
verify\sim\coverage\urgReport\mod3.html
verify\sim\coverage\urgReport\.urg.css
verify\sim\coverage\urgReport\dashboard.html
verify\sim\coverage\urgReport\mod16.html
verify\sim\coverage\urgReport\mod10.html
verify\sim\coverage\urgReport\mod9.html
verify\sim\coverage\urgReport\.sortable.js
verify\sim\coverage\simv.vdb\.cmoptions
verify\sim\coverage\simv.vdb\snps\coverage\db\testdata\rst_tc_1444895275\branch.verilog.data.xml
verify\sim\coverage\simv.vdb\snps\coverage\db\testdata\rst_tc_1444895275\line.verilog.data.xml
verify\sim\coverage\simv.vdb\snps\coverage\db\testdata\rst_tc_1444895275\cond.verilog.data.xml
verify\sim\coverage\simv.vdb\snps\coverage\db\testdata\rst_tc_1444895275\fsm.verilog.data.xml
verify\sim\coverage\simv.vdb\snps\coverage\db\testdata\rst_tc_1444895275\tgl.verilog.data.xml
verify\sim\coverage\simv.vdb\snps\coverage\db\testdata\i2c_rd_err_tc_1444895275\branch.verilog.data.xml
verify\sim\coverage\simv.vdb\snps\coverage\db\testdata\i2c_rd_err_tc_1444895275\line.verilog.data.xml
verify\sim\coverage\simv.vdb\snps\coverage\db\testdata\i2c_rd_err_tc_1444895275\cond.verilog.data.xml
verify\sim\coverage\simv.vdb\snps\coverage\db\testdata\i2c_rd_err_tc_1444895275\fsm.verilog.data.xml
verify\sim\coverage\simv.vdb\snps\coverage\db\testdata\i2c_rd_err_tc_1444895275\tgl.verilog.data.xml
verify\sim\coverage\simv.vdb\snps\coverage\db\testdata\regcfg_tc_1444895218\branch.verilog.data.xml
verify\sim\coverage\simv.vdb\snps\coverage\db\testdata\regcfg_tc_1444895218\line.verilog.data.xml
verify\sim\coverage\simv.vdb\snps\coverage\db\testdata\regcfg_tc_1444895218\cond.verilog.data.xml
verify\sim\coverage\simv.vdb\snps\coverage\db\testdata\regcfg_tc_1444895218\fsm.verilog.data.xml
verify\sim\coverage\simv.vdb\snps\coverage\db\testdata\regcfg_tc_1444895218\tgl.verilog.data.xml
verify\sim\coverage\simv.vdb\snps\coverage\db\testdata\regcfg_tc_1444895989\branch.verilog.data.xml
verify\sim\coverage\simv.vdb\snps\coverage\db\testdata\regcfg_tc_1444895989\line.verilog.data.xml
verify\sim\coverage\simv.vdb\snps\coverage\db\testdata\regcfg_tc_1444895989\cond.verilog.data.xml
verify\sim\coverage\simv.vdb\snps\coverage\db\testdata\regcfg_tc_1444895989\fsm.verilog.data.xml
verify\sim\coverage\simv.vdb\snps\coverage\db\testdata\regcfg_tc_1444895989\tgl.verilog.data.xml
verify\sim\coverage\simv.vdb\snps\coverage\db\testdata\regcfg_tc_1444895337\branch.verilog.data.xml
verify\sim\coverage\simv.vdb\snps\coverage\db\testdata\regcfg_tc_1444895337\line.verilog.data.xml
verify\sim\coverage\simv.vdb\snps\coverage\db\testdata\regcfg_tc_1444895337\cond.verilog.data.xml
verify\sim\coverage\simv.vdb\snps\coverage\db\testdata\regcfg_tc_1444895337\fsm.verilog.data.xml
verify\sim\coverage\simv.vdb\snps\coverage\db\testdata\regcfg_tc_1444895337\tgl.verilog.data.xml
verify\sim\coverage\simv.vdb\snps\coverage\db\testdata\i2c_rd_err_tc_1444895150\branch.verilog.data.xml
verify\sim\coverage\simv.vdb\snps\coverage\db\testdata\i2c_rd_err_tc_1444895150\line.verilog.data.xml
verify\sim\coverage\simv.vdb\snps\coverage\db\testdata\i2c_rd_err_tc_1444895150\cond.verilog.data.xml
verify\sim\coverage\simv.vdb\snps\coverage\db\testdata\i2c_rd_err_tc_1444895150\fsm.verilog.data.xml
verify\sim\coverage\simv.vdb\snps\coverage\db\testdata\i2c_rd_err_tc_1444895150\tgl.verilog.data.xml
verify\sim\coverage\simv.vdb\snps\coverage\db\testdata\i2c_rd_err_tc_1444895444\branch.verilog.data.xml
verify\sim\coverage\simv.vdb\snps\coverage\db\testdata\i2c_rd_err_tc_1444895444\line.verilog.data.xml
verify\sim\coverage\simv.vdb\snps\coverage\db\testdata\i2c_rd_err_tc_1444895444\cond.verilog.data.xml
verify\sim\coverage\simv.vdb\snps\coverage\db\testdata\i2c_rd_err_tc_1444895444\fsm.verilog.data.xml
verify\testcase\roic_base_tc.sv
verify\testcase\adc2spi_tc.sv
verify\testcase\rst_tc.sv
verify\testcase\i2c_dev_addr_tc.sv
verify\testcase\i2c_rd_err_tc.sv
verify\testcase\fifo_overflow_tc.sv
verify\tbench\top.v
verify\tbench\tbench.sv
verify\tbench\top_pad.v
verify\sim\regs_sim.csh
verify\sim\csrc\incr_filespace.db
verify\sim\csrc\Makefile
verify\sim\csrc\Makefile.hsopt
verify\sim\csrc\_vcsobj_archive_info_0.lst
verify\sim\csrc\rmapats.c
verify\sim\csrc\5NrIB_d.o
verify\sim\csrc\SIM_l.o
verify\sim\csrc\rmapats.h
verify\sim\csrc\rmapats_mop.o
verify\sim\csrc\vcspieces.incr
verify\sim\csrc\5NrI_d.o
verify\sim\csrc\_vcs_const_SIM_0.incr.dat
verify\sim\csrc\filelist.dpi
verify\sim\csrc\uvm_dpi.o
verify\sim\csrc\filelist
verify\sim\csrc\filelist.hsopt
verify\sim\csrc\filelist.hsopt.objs
verify\sim\csrc\checksum
verify\sim\csrc\_vcsobj_1_1.a.info
verify\sim\csrc\_vcsobj_1_1.a
verify\sim\csrc\rmapats.o
verify\sim\csrc\rmapats.m
verify\sim\csrc\product_timestamp
verify\sim\csrc\_vcs_etype_SIM_0.incr.dat
verify\sim\verdi.f
verify\sim\run.csh
verify\sim\ucli.key
verify\sim\novas_dump.log
verify\sim\regression.f
verify\sim\cm.log
verify\sim\debug.rc
verify\sim\code_all.f
verify\sim\coverage\urgReport\mod2.html
verify\sim\coverage\urgReport\mod15.html
verify\sim\coverage\urgReport\mod12.html
verify\sim\coverage\urgReport\mod13.html
verify\sim\coverage\urgReport\hierarchy.html
verify\sim\coverage\urgReport\mod7.html
verify\sim\coverage\urgReport\mod11.html
verify\sim\coverage\urgReport\mod21.html
verify\sim\coverage\urgReport\mod17.html
verify\sim\coverage\urgReport\session.xml
verify\sim\coverage\urgReport\mod1.html
verify\sim\coverage\urgReport\mod20.html
verify\sim\coverage\urgReport\modlist.html
verify\sim\coverage\urgReport\mod18.html
verify\sim\coverage\urgReport\tests.html
verify\sim\coverage\urgReport\mod3.html
verify\sim\coverage\urgReport\.urg.css
verify\sim\coverage\urgReport\dashboard.html
verify\sim\coverage\urgReport\mod16.html
verify\sim\coverage\urgReport\mod10.html
verify\sim\coverage\urgReport\mod9.html
verify\sim\coverage\urgReport\.sortable.js
verify\sim\coverage\simv.vdb\.cmoptions
verify\sim\coverage\simv.vdb\snps\coverage\db\testdata\rst_tc_1444895275\branch.verilog.data.xml
verify\sim\coverage\simv.vdb\snps\coverage\db\testdata\rst_tc_1444895275\line.verilog.data.xml
verify\sim\coverage\simv.vdb\snps\coverage\db\testdata\rst_tc_1444895275\cond.verilog.data.xml
verify\sim\coverage\simv.vdb\snps\coverage\db\testdata\rst_tc_1444895275\fsm.verilog.data.xml
verify\sim\coverage\simv.vdb\snps\coverage\db\testdata\rst_tc_1444895275\tgl.verilog.data.xml
verify\sim\coverage\simv.vdb\snps\coverage\db\testdata\i2c_rd_err_tc_1444895275\branch.verilog.data.xml
verify\sim\coverage\simv.vdb\snps\coverage\db\testdata\i2c_rd_err_tc_1444895275\line.verilog.data.xml
verify\sim\coverage\simv.vdb\snps\coverage\db\testdata\i2c_rd_err_tc_1444895275\cond.verilog.data.xml
verify\sim\coverage\simv.vdb\snps\coverage\db\testdata\i2c_rd_err_tc_1444895275\fsm.verilog.data.xml
verify\sim\coverage\simv.vdb\snps\coverage\db\testdata\i2c_rd_err_tc_1444895275\tgl.verilog.data.xml
verify\sim\coverage\simv.vdb\snps\coverage\db\testdata\regcfg_tc_1444895218\branch.verilog.data.xml
verify\sim\coverage\simv.vdb\snps\coverage\db\testdata\regcfg_tc_1444895218\line.verilog.data.xml
verify\sim\coverage\simv.vdb\snps\coverage\db\testdata\regcfg_tc_1444895218\cond.verilog.data.xml
verify\sim\coverage\simv.vdb\snps\coverage\db\testdata\regcfg_tc_1444895218\fsm.verilog.data.xml
verify\sim\coverage\simv.vdb\snps\coverage\db\testdata\regcfg_tc_1444895218\tgl.verilog.data.xml
verify\sim\coverage\simv.vdb\snps\coverage\db\testdata\regcfg_tc_1444895989\branch.verilog.data.xml
verify\sim\coverage\simv.vdb\snps\coverage\db\testdata\regcfg_tc_1444895989\line.verilog.data.xml
verify\sim\coverage\simv.vdb\snps\coverage\db\testdata\regcfg_tc_1444895989\cond.verilog.data.xml
verify\sim\coverage\simv.vdb\snps\coverage\db\testdata\regcfg_tc_1444895989\fsm.verilog.data.xml
verify\sim\coverage\simv.vdb\snps\coverage\db\testdata\regcfg_tc_1444895989\tgl.verilog.data.xml
verify\sim\coverage\simv.vdb\snps\coverage\db\testdata\regcfg_tc_1444895337\branch.verilog.data.xml
verify\sim\coverage\simv.vdb\snps\coverage\db\testdata\regcfg_tc_1444895337\line.verilog.data.xml
verify\sim\coverage\simv.vdb\snps\coverage\db\testdata\regcfg_tc_1444895337\cond.verilog.data.xml
verify\sim\coverage\simv.vdb\snps\coverage\db\testdata\regcfg_tc_1444895337\fsm.verilog.data.xml
verify\sim\coverage\simv.vdb\snps\coverage\db\testdata\regcfg_tc_1444895337\tgl.verilog.data.xml
verify\sim\coverage\simv.vdb\snps\coverage\db\testdata\i2c_rd_err_tc_1444895150\branch.verilog.data.xml
verify\sim\coverage\simv.vdb\snps\coverage\db\testdata\i2c_rd_err_tc_1444895150\line.verilog.data.xml
verify\sim\coverage\simv.vdb\snps\coverage\db\testdata\i2c_rd_err_tc_1444895150\cond.verilog.data.xml
verify\sim\coverage\simv.vdb\snps\coverage\db\testdata\i2c_rd_err_tc_1444895150\fsm.verilog.data.xml
verify\sim\coverage\simv.vdb\snps\coverage\db\testdata\i2c_rd_err_tc_1444895150\tgl.verilog.data.xml
verify\sim\coverage\simv.vdb\snps\coverage\db\testdata\i2c_rd_err_tc_1444895444\branch.verilog.data.xml
verify\sim\coverage\simv.vdb\snps\coverage\db\testdata\i2c_rd_err_tc_1444895444\line.verilog.data.xml
verify\sim\coverage\simv.vdb\snps\coverage\db\testdata\i2c_rd_err_tc_1444895444\cond.verilog.data.xml
verify\sim\coverage\simv.vdb\snps\coverage\db\testdata\i2c_rd_err_tc_1444895444\fsm.verilog.data.xml
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