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文件名称:shiyan

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  • 上传时间:
    2017-08-28
  • 文件大小:
    2.96mb
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介绍说明--下载内容来自于网络,使用问题请自行百度

用verilog语言实现数字中, 在fpga上实现(Using Verilog language to achieve digital, implemented on FPGA)
相关搜索: FPGA 数字时钟

(系统自动生成,下载前可以参看下载内容)

下载文件列表

shiyan
shiyan\clkgen.v
shiyan\clkgen.v.bak
shiyan\db
shiyan\db\logic_util_heursitic.dat
shiyan\db\prev_cmp_smg_interface_demo.qmsg
shiyan\db\smg_interface_demo.amm.cdb
shiyan\db\smg_interface_demo.asm.qmsg
shiyan\db\smg_interface_demo.asm.rdb
shiyan\db\smg_interface_demo.asm_labs.ddb
shiyan\db\smg_interface_demo.cbx.xml
shiyan\db\smg_interface_demo.cmp.bpm
shiyan\db\smg_interface_demo.cmp.cdb
shiyan\db\smg_interface_demo.cmp.hdb
shiyan\db\smg_interface_demo.cmp.kpt
shiyan\db\smg_interface_demo.cmp.logdb
shiyan\db\smg_interface_demo.cmp.rdb
shiyan\db\smg_interface_demo.cmp_merge.kpt
shiyan\db\smg_interface_demo.cycloneive_io_sim_cache.45um_ff_1200mv_0c_fast.hsd
shiyan\db\smg_interface_demo.cycloneive_io_sim_cache.45um_ss_1200mv_0c_slow.hsd
shiyan\db\smg_interface_demo.cycloneive_io_sim_cache.45um_ss_1200mv_85c_slow.hsd
shiyan\db\smg_interface_demo.db_info
shiyan\db\smg_interface_demo.fit.qmsg
shiyan\db\smg_interface_demo.hier_info
shiyan\db\smg_interface_demo.hif
shiyan\db\smg_interface_demo.idb.cdb
shiyan\db\smg_interface_demo.lpc.html
shiyan\db\smg_interface_demo.lpc.rdb
shiyan\db\smg_interface_demo.lpc.txt
shiyan\db\smg_interface_demo.map.bpm
shiyan\db\smg_interface_demo.map.cdb
shiyan\db\smg_interface_demo.map.hdb
shiyan\db\smg_interface_demo.map.kpt
shiyan\db\smg_interface_demo.map.logdb
shiyan\db\smg_interface_demo.map.qmsg
shiyan\db\smg_interface_demo.map_bb.cdb
shiyan\db\smg_interface_demo.map_bb.hdb
shiyan\db\smg_interface_demo.map_bb.logdb
shiyan\db\smg_interface_demo.pre_map.cdb
shiyan\db\smg_interface_demo.pre_map.hdb
shiyan\db\smg_interface_demo.rtlv.hdb
shiyan\db\smg_interface_demo.rtlv_sg.cdb
shiyan\db\smg_interface_demo.rtlv_sg_swap.cdb
shiyan\db\smg_interface_demo.sgdiff.cdb
shiyan\db\smg_interface_demo.sgdiff.hdb
shiyan\db\smg_interface_demo.sld_design_entry.sci
shiyan\db\smg_interface_demo.sld_design_entry_dsc.sci
shiyan\db\smg_interface_demo.smart_action.txt
shiyan\db\smg_interface_demo.sta.qmsg
shiyan\db\smg_interface_demo.sta.rdb
shiyan\db\smg_interface_demo.sta_cmp.8_slow_1200mv_85c.tdb
shiyan\db\smg_interface_demo.syn_hier_info
shiyan\db\smg_interface_demo.tis_db_list.ddb
shiyan\db\smg_interface_demo.tiscmp.fast_1200mv_0c.ddb
shiyan\db\smg_interface_demo.tiscmp.fastest_slow_1200mv_0c.ddb
shiyan\db\smg_interface_demo.tiscmp.fastest_slow_1200mv_85c.ddb
shiyan\db\smg_interface_demo.tiscmp.slow_1200mv_0c.ddb
shiyan\db\smg_interface_demo.tiscmp.slow_1200mv_85c.ddb
shiyan\db\smg_interface_demo.tmw_info
shiyan\disp_dec.v
shiyan\disp_dec.v.bak
shiyan\incremental_db
shiyan\incremental_db\README
shiyan\incremental_db\compiled_partitions
shiyan\incremental_db\compiled_partitions\smg_interface_demo.db_info
shiyan\incremental_db\compiled_partitions\smg_interface_demo.root_partition.cmp.cdb
shiyan\incremental_db\compiled_partitions\smg_interface_demo.root_partition.cmp.dfp
shiyan\incremental_db\compiled_partitions\smg_interface_demo.root_partition.cmp.hdb
shiyan\incremental_db\compiled_partitions\smg_interface_demo.root_partition.cmp.kpt
shiyan\incremental_db\compiled_partitions\smg_interface_demo.root_partition.cmp.logdb
shiyan\incremental_db\compiled_partitions\smg_interface_demo.root_partition.cmp.rcfdb
shiyan\incremental_db\compiled_partitions\smg_interface_demo.root_partition.map.cdb
shiyan\incremental_db\compiled_partitions\smg_interface_demo.root_partition.map.dpi
shiyan\incremental_db\compiled_partitions\smg_interface_demo.root_partition.map.hbdb.cdb
shiyan\incremental_db\compiled_partitions\smg_interface_demo.root_partition.map.hbdb.hb_info
shiyan\incremental_db\compiled_partitions\smg_interface_demo.root_partition.map.hbdb.hdb
shiyan\incremental_db\compiled_partitions\smg_interface_demo.root_partition.map.hbdb.sig
shiyan\incremental_db\compiled_partitions\smg_interface_demo.root_partition.map.hdb
shiyan\incremental_db\compiled_partitions\smg_interface_demo.root_partition.map.kpt
shiyan\int_div.v
shiyan\myclock.v
shiyan\myclock.v.bak
shiyan\smg_control_module.v
shiyan\smg_encode_module.v
shiyan\smg_interface.v
shiyan\smg_interface_demo.asm.rpt
shiyan\smg_interface_demo.cdf
shiyan\smg_interface_demo.done
shiyan\smg_interface_demo.fit.rpt
shiyan\smg_interface_demo.fit.smsg
shiyan\smg_interface_demo.fit.summary
shiyan\smg_interface_demo.flow.rpt
shiyan\smg_interface_demo.map.rpt
shiyan\smg_interface_demo.map.smsg
shiyan\smg_interface_demo.map.summary
shiyan\smg_interface_demo.pin
shiyan\smg_interface_demo.qpf
shiyan\smg_interface_demo.qsf
shiyan\smg_interface_demo.sof
shiyan\smg_interface_demo.sta.rpt

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