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文件名称:S02_CH10_AXI_User_GPIO

  • 所属分类：
    VHDL/FPGA/Verilog
  • 标签属性：
    [PDF]
  • 上传时间：
    2017-09-10
  • 文件大小：
    38.48mb
  • 已下载：
    0次
  • 提 供 者：
    wudu****
  • 相关连接：
    无
  • 下载说明：
    别用迅雷下载，失败请重下，重下不扣分！
修正介绍说明

介绍说明－－下载内容来自于网络，使用问题请自行百度

An example design of Zynq GPIO (zynq7010 board)
相关搜索： ZYNQ7000 fpga verilog

(系统自动生成,下载前可以参看下载内容)

下载文件列表

CH10_AXI_User_GPIO/DOC/AXI4整理.doc
CH10_AXI_User_GPIO/DOC/MiZ7010N_CORE_20161215.pdf
CH10_AXI_User_GPIO/DOC/Miz701N_fun20161215.pdf
CH10_AXI_User_GPIO/DOC/readme.txt
CH10_AXI_User_GPIO/DOC/ug585-Zynq-7000-TRM.pdf
CH10_AXI_User_GPIO/Miz_ip_lib/GPIO_LITE_ML/component.xml
CH10_AXI_User_GPIO/Miz_ip_lib/GPIO_LITE_ML/GPIO_LITE_ML/GPIO_LITE_ML.cache/wt/java_command_handlers.wdf
CH10_AXI_User_GPIO/Miz_ip_lib/GPIO_LITE_ML/GPIO_LITE_ML/GPIO_LITE_ML.cache/wt/project.wpc
CH10_AXI_User_GPIO/Miz_ip_lib/GPIO_LITE_ML/GPIO_LITE_ML/GPIO_LITE_ML.cache/wt/synthesis.wdf
CH10_AXI_User_GPIO/Miz_ip_lib/GPIO_LITE_ML/GPIO_LITE_ML/GPIO_LITE_ML.cache/wt/synthesis_details.wdf
CH10_AXI_User_GPIO/Miz_ip_lib/GPIO_LITE_ML/GPIO_LITE_ML/GPIO_LITE_ML.cache/wt/webtalk_pa.xml
CH10_AXI_User_GPIO/Miz_ip_lib/GPIO_LITE_ML/GPIO_LITE_ML/GPIO_LITE_ML.hw/GPIO_LITE_ML.lpr
CH10_AXI_User_GPIO/Miz_ip_lib/GPIO_LITE_ML/GPIO_LITE_ML/GPIO_LITE_ML.runs/.jobs/vrs_config_1.xml
CH10_AXI_User_GPIO/Miz_ip_lib/GPIO_LITE_ML/GPIO_LITE_ML/GPIO_LITE_ML.runs/synth_1/.vivado.begin.rst
CH10_AXI_User_GPIO/Miz_ip_lib/GPIO_LITE_ML/GPIO_LITE_ML/GPIO_LITE_ML.runs/synth_1/.vivado.end.rst
CH10_AXI_User_GPIO/Miz_ip_lib/GPIO_LITE_ML/GPIO_LITE_ML/GPIO_LITE_ML.runs/synth_1/.Vivado_Synthesis.queue.rst
CH10_AXI_User_GPIO/Miz_ip_lib/GPIO_LITE_ML/GPIO_LITE_ML/GPIO_LITE_ML.runs/synth_1/gen_run.xml
CH10_AXI_User_GPIO/Miz_ip_lib/GPIO_LITE_ML/GPIO_LITE_ML/GPIO_LITE_ML.runs/synth_1/GPIO_LITE_ML.dcp
CH10_AXI_User_GPIO/Miz_ip_lib/GPIO_LITE_ML/GPIO_LITE_ML/GPIO_LITE_ML.runs/synth_1/GPIO_LITE_ML.tcl
CH10_AXI_User_GPIO/Miz_ip_lib/GPIO_LITE_ML/GPIO_LITE_ML/GPIO_LITE_ML.runs/synth_1/GPIO_LITE_ML.vds
CH10_AXI_User_GPIO/Miz_ip_lib/GPIO_LITE_ML/GPIO_LITE_ML/GPIO_LITE_ML.runs/synth_1/GPIO_LITE_ML_utilization_synth.pb
CH10_AXI_User_GPIO/Miz_ip_lib/GPIO_LITE_ML/GPIO_LITE_ML/GPIO_LITE_ML.runs/synth_1/GPIO_LITE_ML_utilization_synth.rpt
CH10_AXI_User_GPIO/Miz_ip_lib/GPIO_LITE_ML/GPIO_LITE_ML/GPIO_LITE_ML.runs/synth_1/htr.txt
CH10_AXI_User_GPIO/Miz_ip_lib/GPIO_LITE_ML/GPIO_LITE_ML/GPIO_LITE_ML.runs/synth_1/ISEWrap.js
CH10_AXI_User_GPIO/Miz_ip_lib/GPIO_LITE_ML/GPIO_LITE_ML/GPIO_LITE_ML.runs/synth_1/ISEWrap.sh
CH10_AXI_User_GPIO/Miz_ip_lib/GPIO_LITE_ML/GPIO_LITE_ML/GPIO_LITE_ML.runs/synth_1/project.wdf
CH10_AXI_User_GPIO/Miz_ip_lib/GPIO_LITE_ML/GPIO_LITE_ML/GPIO_LITE_ML.runs/synth_1/rundef.js
CH10_AXI_User_GPIO/Miz_ip_lib/GPIO_LITE_ML/GPIO_LITE_ML/GPIO_LITE_ML.runs/synth_1/runme.bat
CH10_AXI_User_GPIO/Miz_ip_lib/GPIO_LITE_ML/GPIO_LITE_ML/GPIO_LITE_ML.runs/synth_1/runme.log
CH10_AXI_User_GPIO/Miz_ip_lib/GPIO_LITE_ML/GPIO_LITE_ML/GPIO_LITE_ML.runs/synth_1/runme.sh
CH10_AXI_User_GPIO/Miz_ip_lib/GPIO_LITE_ML/GPIO_LITE_ML/GPIO_LITE_ML.runs/synth_1/vivado.jou
CH10_AXI_User_GPIO/Miz_ip_lib/GPIO_LITE_ML/GPIO_LITE_ML/GPIO_LITE_ML.runs/synth_1/vivado.pb
CH10_AXI_User_GPIO/Miz_ip_lib/GPIO_LITE_ML/GPIO_LITE_ML/GPIO_LITE_ML.xpr
CH10_AXI_User_GPIO/Miz_ip_lib/GPIO_LITE_ML/GPIO_LITE_ML/vivado.jou
CH10_AXI_User_GPIO/Miz_ip_lib/GPIO_LITE_ML/GPIO_LITE_ML/vivado.log
CH10_AXI_User_GPIO/Miz_ip_lib/GPIO_LITE_ML/IPSRC/GPIO_LITE_ML.v
CH10_AXI_User_GPIO/Miz_ip_lib/GPIO_LITE_ML/IPSRC/GPIO_LITE_ML_v1_0_S00_AXI.v
CH10_AXI_User_GPIO/Miz_ip_lib/GPIO_LITE_ML/xgui/GPIO_LITE_ML_v1_0.tcl
CH10_AXI_User_GPIO/Miz_ip_lib/LED_ML/component.xml
CH10_AXI_User_GPIO/Miz_ip_lib/LED_ML/IPSRC/LED_ML.v
CH10_AXI_User_GPIO/Miz_ip_lib/LED_ML/Miz_ip/Miz_ip.cache/wt/java_command_handlers.wdf
CH10_AXI_User_GPIO/Miz_ip_lib/LED_ML/Miz_ip/Miz_ip.cache/wt/project.wpc
CH10_AXI_User_GPIO/Miz_ip_lib/LED_ML/Miz_ip/Miz_ip.cache/wt/synthesis.wdf
CH10_AXI_User_GPIO/Miz_ip_lib/LED_ML/Miz_ip/Miz_ip.cache/wt/synthesis_details.wdf
CH10_AXI_User_GPIO/Miz_ip_lib/LED_ML/Miz_ip/Miz_ip.cache/wt/webtalk_pa.xml
CH10_AXI_User_GPIO/Miz_ip_lib/LED_ML/Miz_ip/Miz_ip.hw/Miz_ip.lpr
CH10_AXI_User_GPIO/Miz_ip_lib/LED_ML/Miz_ip/Miz_ip.runs/.jobs/vrs_config_1.xml
CH10_AXI_User_GPIO/Miz_ip_lib/LED_ML/Miz_ip/Miz_ip.runs/.jobs/vrs_config_2.xml
CH10_AXI_User_GPIO/Miz_ip_lib/LED_ML/Miz_ip/Miz_ip.runs/synth_1/.vivado.begin.rst
CH10_AXI_User_GPIO/Miz_ip_lib/LED_ML/Miz_ip/Miz_ip.runs/synth_1/.vivado.end.rst
CH10_AXI_User_GPIO/Miz_ip_lib/LED_ML/Miz_ip/Miz_ip.runs/synth_1/.Vivado_Synthesis.queue.rst
CH10_AXI_User_GPIO/Miz_ip_lib/LED_ML/Miz_ip/Miz_ip.runs/synth_1/gen_run.xml
CH10_AXI_User_GPIO/Miz_ip_lib/LED_ML/Miz_ip/Miz_ip.runs/synth_1/htr.txt
CH10_AXI_User_GPIO/Miz_ip_lib/LED_ML/Miz_ip/Miz_ip.runs/synth_1/ISEWrap.js
CH10_AXI_User_GPIO/Miz_ip_lib/LED_ML/Miz_ip/Miz_ip.runs/synth_1/ISEWrap.sh
CH10_AXI_User_GPIO/Miz_ip_lib/LED_ML/Miz_ip/Miz_ip.runs/synth_1/LED_ML.dcp
CH10_AXI_User_GPIO/Miz_ip_lib/LED_ML/Miz_ip/Miz_ip.runs/synth_1/LED_ML.tcl
CH10_AXI_User_GPIO/Miz_ip_lib/LED_ML/Miz_ip/Miz_ip.runs/synth_1/LED_ML.vds
CH10_AXI_User_GPIO/Miz_ip_lib/LED_ML/Miz_ip/Miz_ip.runs/synth_1/LED_ML_utilization_synth.pb
CH10_AXI_User_GPIO/Miz_ip_lib/LED_ML/Miz_ip/Miz_ip.runs/synth_1/LED_ML_utilization_synth.rpt
CH10_AXI_User_GPIO/Miz_ip_lib/LED_ML/Miz_ip/Miz_ip.runs/synth_1/project.wdf
CH10_AXI_User_GPIO/Miz_ip_lib/LED_ML/Miz_ip/Miz_ip.runs/synth_1/rundef.js
CH10_AXI_User_GPIO/Miz_ip_lib/LED_ML/Miz_ip/Miz_ip.runs/synth_1/runme.bat
CH10_AXI_User

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