CDN加速镜像 | 设为首页 | 加入收藏夹
登陆 | 会员注册
当前位置： 首页 资源下载 源码下载 嵌入式/单片机编程 VHDL编程
收藏

文件名称:cpu

  • 所属分类：
    VHDL/FPGA/Verilog
  • 标签属性：
    [PDF]
  • 上传时间：
    2017-09-12
  • 文件大小：
    4.11mb
  • 已下载：
    0次
  • 提 供 者：
    Kevi****
  • 相关连接：
    无
  • 下载说明：
    别用迅雷下载，失败请重下，重下不扣分！
修正介绍说明

介绍说明－－下载内容来自于网络，使用问题请自行百度

Simulating the work of cpu.(Simulating the work theory of cpu. By VHDL in ISE.)
相关搜索： vhdl cpu

(系统自动生成,下载前可以参看下载内容)

下载文件列表

cpu
cpu\.Xil-PlanAhead-4812-P002
cpu\.Xil-PlanAhead-4812-P002\ngc2edif
cpu\.Xil-PlanAhead-4812-P002\ngc2edif\memory.edif
cpu\.Xil-PlanAhead-4812-P002\ngc2edif\ngc2edif.log
cpu\.Xil-PlanAhead-4812-P002\ngc2edif\TOP.edif
cpu\.Xil-PlanAhead-4812-P002\ngc2edif\_xmsgs
cpu\.Xil-PlanAhead-4812-P002\ngc2edif\_xmsgs\ngc2edif.xmsgs
cpu\1-100.coe
cpu\ACC.cmd_log
cpu\ACC.spl
cpu\ACC.sym
cpu\ACC.vhd
cpu\ALU.vhd
cpu\BR.vhd
cpu\CAR.vhd
cpu\cpu
cpu\cpu.gise
cpu\cpu.xise
cpu\cpu\alu.vhd
cpu\cpu\br.vhd
cpu\cpu\cpu.gise
cpu\cpu\cpu.xise
cpu\cpu\cpu_ise12migration.zip
cpu\cpu\cu.vhd
cpu\cpu\display.vhd
cpu\cpu\ipcore_dir
cpu\cpu\ipcore_dir\blk_mem_gen_ds512.pdf
cpu\cpu\ipcore_dir\blk_mem_gen_v6_3
cpu\cpu\ipcore_dir\blk_mem_gen_v6_3.asy
cpu\cpu\ipcore_dir\blk_mem_gen_v6_3.gise
cpu\cpu\ipcore_dir\blk_mem_gen_v6_3.mif
cpu\cpu\ipcore_dir\blk_mem_gen_v6_3.ngc
cpu\cpu\ipcore_dir\blk_mem_gen_v6_3.sym
cpu\cpu\ipcore_dir\blk_mem_gen_v6_3.v
cpu\cpu\ipcore_dir\blk_mem_gen_v6_3.veo
cpu\cpu\ipcore_dir\blk_mem_gen_v6_3.xco
cpu\cpu\ipcore_dir\blk_mem_gen_v6_3.xise
cpu\cpu\ipcore_dir\blk_mem_gen_v6_3\example_design
cpu\cpu\ipcore_dir\blk_mem_gen_v6_3\example_design\blk_mem_gen_v6_3_top.ucf
cpu\cpu\ipcore_dir\blk_mem_gen_v6_3\example_design\blk_mem_gen_v6_3_top.vhd
cpu\cpu\ipcore_dir\blk_mem_gen_v6_3\example_design\blk_mem_gen_v6_3_top.xdc
cpu\cpu\ipcore_dir\blk_mem_gen_v6_3\example_design\bmg_wrapper.vhd
cpu\cpu\ipcore_dir\blk_mem_gen_v6_3\implement
cpu\cpu\ipcore_dir\blk_mem_gen_v6_3\implement\implement.bat
cpu\cpu\ipcore_dir\blk_mem_gen_v6_3\implement\implement.sh
cpu\cpu\ipcore_dir\blk_mem_gen_v6_3\implement\planAhead_rdn.bat
cpu\cpu\ipcore_dir\blk_mem_gen_v6_3\implement\planAhead_rdn.sh
cpu\cpu\ipcore_dir\blk_mem_gen_v6_3\implement\planAhead_rdn.tcl
cpu\cpu\ipcore_dir\blk_mem_gen_v6_3\implement\xst.prj
cpu\cpu\ipcore_dir\blk_mem_gen_v6_3\implement\xst.scr
cpu\cpu\ipcore_dir\blk_mem_gen_v6_3\simulation
cpu\cpu\ipcore_dir\blk_mem_gen_v6_3\simulation\addr_gen.vhd
cpu\cpu\ipcore_dir\blk_mem_gen_v6_3\simulation\bmg_stim_gen.vhd
cpu\cpu\ipcore_dir\blk_mem_gen_v6_3\simulation\bmg_tb_pkg.vhd
cpu\cpu\ipcore_dir\blk_mem_gen_v6_3\simulation\bmg_tb_synth.vhd
cpu\cpu\ipcore_dir\blk_mem_gen_v6_3\simulation\bmg_tb_top.vhd
cpu\cpu\ipcore_dir\blk_mem_gen_v6_3\simulation\checker.vhd
cpu\cpu\ipcore_dir\blk_mem_gen_v6_3\simulation\data_gen.vhd
cpu\cpu\ipcore_dir\blk_mem_gen_v6_3\simulation\functional
cpu\cpu\ipcore_dir\blk_mem_gen_v6_3\simulation\functional\isim_tcl_cmds.tcl
cpu\cpu\ipcore_dir\blk_mem_gen_v6_3\simulation\functional\simulate_isim.bat
cpu\cpu\ipcore_dir\blk_mem_gen_v6_3\simulation\functional\simulate_mti.do
cpu\cpu\ipcore_dir\blk_mem_gen_v6_3\simulation\functional\simulate_ncsim.sh
cpu\cpu\ipcore_dir\blk_mem_gen_v6_3\simulation\functional\wave_mti.do
cpu\cpu\ipcore_dir\blk_mem_gen_v6_3\simulation\functional\wave_ncsim.sv
cpu\cpu\ipcore_dir\blk_mem_gen_v6_3\simulation\random.vhd
cpu\cpu\ipcore_dir\blk_mem_gen_v6_3\simulation\timing
cpu\cpu\ipcore_dir\blk_mem_gen_v6_3\simulation\timing\isim_tcl_cmds.tcl
cpu\cpu\ipcore_dir\blk_mem_gen_v6_3\simulation\timing\simulate_isim.bat
cpu\cpu\ipcore_dir\blk_mem_gen_v6_3\simulation\timing\simulate_mti.do
cpu\cpu\ipcore_dir\blk_mem_gen_v6_3\simulation\timing\simulate_ncsim.sh
cpu\cpu\ipcore_dir\blk_mem_gen_v6_3\simulation\timing\wave_mti.do
cpu\cpu\ipcore_dir\blk_mem_gen_v6_3\simulation\timing\wave_ncsim.sv
cpu\cpu\ipcore_dir\blk_mem_gen_v6_3_flist.txt
cpu\cpu\ipcore_dir\blk_mem_gen_v6_3_readme.txt
cpu\cpu\ipcore_dir\blk_mem_gen_v6_3_xmdf.tcl
cpu\cpu\ipcore_dir\coregen.cgp
cpu\cpu\ipcore_dir\coregen.log
cpu\cpu\ipcore_dir\create_memory.tcl
cpu\cpu\ipcore_dir\edit_memory.tcl
cpu\cpu\ipcore_dir\memory
cpu\cpu\ipcore_dir\memory.asy
cpu\cpu\ipcore_dir\memory.gise
cpu\cpu\ipcore_dir\memory.mif
cpu\cpu\ipcore_dir\memory.ncf
cpu\cpu\ipcore_dir\memory.ngc
cpu\cpu\ipcore_dir\memory.sym
cpu\cpu\ipcore_dir\memory.v
cpu\cpu\ipcore_dir\memory.veo
cpu\cpu\ipcore_dir\memory.xco
cpu\cpu\ipcore_dir\memory.xise
cpu\cpu\ipcore_dir\memory\example_design
cpu\cpu\ipcore_dir\memory\example_design\bmg_wrapper.vhd
cpu\cpu\ipcore_dir\memory\example_design\memory_top.ucf
cpu\cpu\ipcore_dir\memory\example_design\memory_top.vhd
cpu\cpu\ipcore_dir\memory\example_design\memory_top.xdc
cpu\cpu\ipcore_dir\memory\implement
cpu\cpu\ipcore_dir\memory\implement\implement.bat
cpu\cpu\ipcore_dir\memory\implement\implement.sh

相关说明

  • 本站资源为会员上传分享交流与学习,如有侵犯您的权益,请联系我们删除.
  • 搜珍网是交换下载平台，只提供交流渠道，下载内容来自于网络，除下载问题外，其它问题请自行百度。更多...
  • 本站已设置防盗链，请勿用迅雷、QQ旋风等下载软件下载资源，下载后用WinRAR最新版进行解压.
  • 如果您发现内容无法下载，请稍后再次尝试；或换浏览器；或者到消费记录里找到下载记录反馈给我们.
  • 下载后发现下载的内容跟说明不相乎，请到消费记录里找到下载记录反馈给我们，经确认后退回积分.
  • 如下载前有疑问，可以通过点击"提供者"的名字，查看对方的联系方式，联系对方咨询.
查看所有评论

相关评论

暂无评论内容．

发表评论

*快速评论： 推荐 一般 有密码 和说明不符 不是源码或资料 文件不全 不能解压 纯粹是垃圾
*内　　容：
*验 证 码：
搜珍网 www.dssz.com

浏览历史记录

关闭