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文件名称:dianzhen

  • 所属分类：
    VHDL/FPGA/Verilog
  • 标签属性：
    [VHDL] [源码]
  • 上传时间：
    2017-09-12
  • 文件大小：
    12.15mb
  • 已下载：
    0次
  • 提 供 者：
    社*****
  • 相关连接：
    无
  • 下载说明：
    别用迅雷下载，失败请重下，重下不扣分！
修正介绍说明

介绍说明－－下载内容来自于网络，使用问题请自行百度

课程设计:FPGA驱动16*16点阵实现图片显示及贪吃蛇游戏，含点阵PCB。(Curriculum design: FPGA driver, 16*16 dot matrix, picture display and Snake games, including dot matrix PCB.)
相关搜索： fpga pcb

(系统自动生成,下载前可以参看下载内容)

下载文件列表

dianzhen
dianzhen\PCB
dianzhen\PCB\PCB_Project
dianzhen\PCB\PCB_Project\PCB1.PcbDoc
dianzhen\PCB\PCB_Project\PcbLib1.PcbLib
dianzhen\PCB\PCB_Project\PCB_Project.PrjPcb
dianzhen\PCB\PCB_Project\Schlib1.SchLib
dianzhen\PCB\PCB_Project\Sheet1.SchDoc
dianzhen\PCB\PCB_Project\__Previews
dianzhen\PCB\PCB_Project\__Previews\PCB1.PcbDocPreview
dianzhen\PCB\PCB_Project\__Previews\Sheet1.SchDocPreview
dianzhen\project
dianzhen\project\.qsys_edit
dianzhen\project\.qsys_edit\filters.xml
dianzhen\project\.qsys_edit\preferences.xml
dianzhen\project\db
dianzhen\project\db\.cmp.kpt
dianzhen\project\db\altsyncram_7ga1.tdf
dianzhen\project\db\altsyncram_j3g1.tdf
dianzhen\project\db\altsyncram_s4g1.tdf
dianzhen\project\db\altsyncram_uea1.tdf
dianzhen\project\db\logic_util_heursitic.dat
dianzhen\project\db\MyProject.ace_cmp.bpm
dianzhen\project\db\MyProject.ace_cmp.cdb
dianzhen\project\db\MyProject.ace_cmp.hdb
dianzhen\project\db\MyProject.asm.qmsg
dianzhen\project\db\MyProject.asm.rdb
dianzhen\project\db\MyProject.asm_labs.ddb
dianzhen\project\db\MyProject.atom_fit.nvd
dianzhen\project\db\MyProject.atom_map.nvd
dianzhen\project\db\MyProject.cbx.xml
dianzhen\project\db\MyProject.cmp.bpm
dianzhen\project\db\MyProject.cmp.cdb
dianzhen\project\db\MyProject.cmp.hdb
dianzhen\project\db\MyProject.cmp.idb
dianzhen\project\db\MyProject.cmp.logdb
dianzhen\project\db\MyProject.cmp.rdb
dianzhen\project\db\MyProject.cmp_merge.kpt
dianzhen\project\db\MyProject.cuda_io_sim_cache.45um_ff_1200mv_0c_fast.hsd
dianzhen\project\db\MyProject.cuda_io_sim_cache.45um_ss_1200mv_85c_slow.hsd
dianzhen\project\db\MyProject.cycloneive_io_sim_cache.45um_ff_1200mv_0c_fast.hsd
dianzhen\project\db\MyProject.cycloneive_io_sim_cache.45um_ff_1200mv_n40c_fast.hsd
dianzhen\project\db\MyProject.cycloneive_io_sim_cache.45um_ii_1200mv_100c_slow.hsd
dianzhen\project\db\MyProject.cycloneive_io_sim_cache.45um_ii_1200mv_85c_slow.hsd
dianzhen\project\db\MyProject.cycloneive_io_sim_cache.45um_ii_1200mv_n40c_slow.hsd
dianzhen\project\db\MyProject.cycloneive_io_sim_cache.45um_ss_1200mv_0c_slow.hsd
dianzhen\project\db\MyProject.cycloneive_io_sim_cache.45um_ss_1200mv_85c_slow.hsd
dianzhen\project\db\MyProject.db_info
dianzhen\project\db\MyProject.eco.cdb
dianzhen\project\db\MyProject.eda.qmsg
dianzhen\project\db\MyProject.fit.qmsg
dianzhen\project\db\MyProject.hier_info
dianzhen\project\db\MyProject.hif
dianzhen\project\db\MyProject.ipinfo
dianzhen\project\db\MyProject.lpc.html
dianzhen\project\db\MyProject.lpc.rdb
dianzhen\project\db\MyProject.lpc.txt
dianzhen\project\db\MyProject.map.ammdb
dianzhen\project\db\MyProject.map.bpm
dianzhen\project\db\MyProject.map.cdb
dianzhen\project\db\MyProject.map.hdb
dianzhen\project\db\MyProject.map.kpt
dianzhen\project\db\MyProject.map.logdb
dianzhen\project\db\MyProject.map.qmsg
dianzhen\project\db\MyProject.map.rdb
dianzhen\project\db\MyProject.map_bb.cdb
dianzhen\project\db\MyProject.map_bb.hdb
dianzhen\project\db\MyProject.map_bb.logdb
dianzhen\project\db\MyProject.npp.qmsg
dianzhen\project\db\MyProject.pplq.rdb
dianzhen\project\db\MyProject.pre_map.hdb
dianzhen\project\db\MyProject.pti_db_list.ddb
dianzhen\project\db\MyProject.qns
dianzhen\project\db\MyProject.root_partition.map.reg_db.cdb
dianzhen\project\db\MyProject.routing.rdb
dianzhen\project\db\MyProject.rtlv.hdb
dianzhen\project\db\MyProject.rtlv_sg.cdb
dianzhen\project\db\MyProject.rtlv_sg_swap.cdb
dianzhen\project\db\MyProject.sgate.nvd
dianzhen\project\db\MyProject.sgate_sm.nvd
dianzhen\project\db\MyProject.sgate_sm_bdd.nvd
dianzhen\project\db\MyProject.sgdiff.cdb
dianzhen\project\db\MyProject.sgdiff.hdb
dianzhen\project\db\MyProject.sld_design_entry.sci
dianzhen\project\db\MyProject.sld_design_entry_dsc.sci
dianzhen\project\db\MyProject.smart_action.txt
dianzhen\project\db\MyProject.smp_dump.txt
dianzhen\project\db\MyProject.sta.qmsg
dianzhen\project\db\MyProject.sta.rdb
dianzhen\project\db\MyProject.sta_cmp.7_slow_1200mv_100c.tdb
dianzhen\project\db\MyProject.tiscmp.fastest_slow_1200mv_85c.ddb
dianzhen\project\db\MyProject.tiscmp.fastest_slow_1200mv_n40c.ddb
dianzhen\project\db\MyProject.tiscmp.fast_1200mv_n40c.ddb
dianzhen\project\db\MyProject.tiscmp.slow_1200mv_100c.ddb
dianzhen\project\db\MyProject.tiscmp.slow_1200mv_n40c.ddb
dianzhen\project\db\MyProject.tis_db_list.ddb
dianzhen\project\db\MyProject.tmw_info
dianzhen\project\db\MyProject.vpr.ammdb
dianzhen\project\db\My_PLL_altpll.v
dianzhen\project\db\prev_cmp_MyProject.qmsg

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