文件名称:bingo_spi_test
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- 上传时间:2017-09-25
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文件大小:52kb
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利用SPI实现FPGA和外设之间的通信。经过Modelsim仿真验证。(为FPGA设计技巧与案例开发详解一书源码)(Using SPI to implement communication between FPGA and peripheral. After Modelsim simulation verification. (for FPGA design techniques and case development detailed explanation of a book source))
相关搜索: verilog/SPI通信
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下载文件列表
bingo_spi_test\design\pll_system_ctrl.v
bingo_spi_test\design\spi_receicer.v
bingo_spi_test\design\spi_transfer.v
bingo_spi_test\design\system_init_delay.v
bingo_spi_test\sim\run .do
bingo_spi_test\sim\tb_spi_receiver.cr.mti
bingo_spi_test\sim\tb_spi_receiver.mpf
bingo_spi_test\sim\tb_spi_receiver.v
bingo_spi_test\sim\vsim.wlf
bingo_spi_test\sim\work\spi_receiver\verilog.asm64
bingo_spi_test\sim\work\spi_receiver\verilog.rw64
bingo_spi_test\sim\work\spi_receiver\_primary.dat
bingo_spi_test\sim\work\spi_receiver\_primary.dbs
bingo_spi_test\sim\work\spi_receiver\_primary.vhd
bingo_spi_test\sim\work\spi_transfer\verilog.asm64
bingo_spi_test\sim\work\spi_transfer\verilog.rw64
bingo_spi_test\sim\work\spi_transfer\_primary.dat
bingo_spi_test\sim\work\spi_transfer\_primary.dbs
bingo_spi_test\sim\work\spi_transfer\_primary.vhd
bingo_spi_test\sim\work\tb_spi_receiver\verilog.asm64
bingo_spi_test\sim\work\tb_spi_receiver\verilog.rw64
bingo_spi_test\sim\work\tb_spi_receiver\_primary.dat
bingo_spi_test\sim\work\tb_spi_receiver\_primary.dbs
bingo_spi_test\sim\work\tb_spi_receiver\_primary.vhd
bingo_spi_test\sim\work\_info
bingo_spi_test\sim\work\_temp\vlog1ndadr
bingo_spi_test\sim\work\_temp\vlog3yiawb
bingo_spi_test\sim\work\_temp\vlog98w4gz
bingo_spi_test\sim\work\_vmake
bingo_spi_test\sim\work\spi_receiver
bingo_spi_test\sim\work\spi_transfer
bingo_spi_test\sim\work\tb_spi_receiver
bingo_spi_test\sim\work\_temp
bingo_spi_test\sim\work
bingo_spi_test\design
bingo_spi_test\docunment
bingo_spi_test\quartus_prj
bingo_spi_test\sim
bingo_spi_test
bingo_spi_test\design\spi_receicer.v
bingo_spi_test\design\spi_transfer.v
bingo_spi_test\design\system_init_delay.v
bingo_spi_test\sim\run .do
bingo_spi_test\sim\tb_spi_receiver.cr.mti
bingo_spi_test\sim\tb_spi_receiver.mpf
bingo_spi_test\sim\tb_spi_receiver.v
bingo_spi_test\sim\vsim.wlf
bingo_spi_test\sim\work\spi_receiver\verilog.asm64
bingo_spi_test\sim\work\spi_receiver\verilog.rw64
bingo_spi_test\sim\work\spi_receiver\_primary.dat
bingo_spi_test\sim\work\spi_receiver\_primary.dbs
bingo_spi_test\sim\work\spi_receiver\_primary.vhd
bingo_spi_test\sim\work\spi_transfer\verilog.asm64
bingo_spi_test\sim\work\spi_transfer\verilog.rw64
bingo_spi_test\sim\work\spi_transfer\_primary.dat
bingo_spi_test\sim\work\spi_transfer\_primary.dbs
bingo_spi_test\sim\work\spi_transfer\_primary.vhd
bingo_spi_test\sim\work\tb_spi_receiver\verilog.asm64
bingo_spi_test\sim\work\tb_spi_receiver\verilog.rw64
bingo_spi_test\sim\work\tb_spi_receiver\_primary.dat
bingo_spi_test\sim\work\tb_spi_receiver\_primary.dbs
bingo_spi_test\sim\work\tb_spi_receiver\_primary.vhd
bingo_spi_test\sim\work\_info
bingo_spi_test\sim\work\_temp\vlog1ndadr
bingo_spi_test\sim\work\_temp\vlog3yiawb
bingo_spi_test\sim\work\_temp\vlog98w4gz
bingo_spi_test\sim\work\_vmake
bingo_spi_test\sim\work\spi_receiver
bingo_spi_test\sim\work\spi_transfer
bingo_spi_test\sim\work\tb_spi_receiver
bingo_spi_test\sim\work\_temp
bingo_spi_test\sim\work
bingo_spi_test\design
bingo_spi_test\docunment
bingo_spi_test\quartus_prj
bingo_spi_test\sim
bingo_spi_test
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