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文件名称:CPU-master

  • 所属分类：
    微处理器开发
  • 标签属性：
    [JavaScript] [源码]
  • 上传时间：
    2017-11-06
  • 文件大小：
    56kb
  • 已下载：
    0次
  • 提 供 者：
    9901****
  • 相关连接：
    无
  • 下载说明：
    别用迅雷下载，失败请重下，重下不扣分！
修正介绍说明

介绍说明－－下载内容来自于网络，使用问题请自行百度

单周期CPU的Verilog源码实现，基于Vivado(Single cycle CPU Verilog source code implementation, based on Vivado)
相关搜索： cpu 单周期 verilog vivado

(系统自动生成,下载前可以参看下载内容)

下载文件列表

CPU-master
CPU-master\.gitattributes
CPU-master\.gitignore
CPU-master\MCPU
CPU-master\MCPU\MCPU.hw
CPU-master\MCPU\MCPU.hw\MCPU.lpr
CPU-master\MCPU\MCPU.ip_user_files
CPU-master\MCPU\MCPU.ip_user_files\README.txt
CPU-master\MCPU\MCPU.ip_user_files\mem_init_files
CPU-master\MCPU\MCPU.ip_user_files\mem_init_files\Inst.mem
CPU-master\MCPU\MCPU.runs
CPU-master\MCPU\MCPU.runs\impl_1
CPU-master\MCPU\MCPU.runs\impl_1\htr.txt
CPU-master\MCPU\MCPU.runs\synth_1
CPU-master\MCPU\MCPU.runs\synth_1\.Xil
CPU-master\MCPU\MCPU.runs\synth_1\.Xil\Basys_propImpl.xdc
CPU-master\MCPU\MCPU.runs\synth_1\fsm_encoding.os
CPU-master\MCPU\MCPU.runs\synth_1\htr.txt
CPU-master\MCPU\MCPU.sim
CPU-master\MCPU\MCPU.sim\sim_1
CPU-master\MCPU\MCPU.sim\sim_1\behav
CPU-master\MCPU\MCPU.sim\sim_1\behav\Inst.mem
CPU-master\MCPU\MCPU.sim\sim_1\behav\SIM_vlog.prj
CPU-master\MCPU\MCPU.sim\sim_1\behav\xsim.ini
CPU-master\MCPU\MCPU.srcs
CPU-master\MCPU\MCPU.srcs\constrs_1
CPU-master\MCPU\MCPU.srcs\constrs_1\new
CPU-master\MCPU\MCPU.srcs\constrs_1\new\Con1.xdc
CPU-master\MCPU\MCPU.srcs\sim_1
CPU-master\MCPU\MCPU.srcs\sim_1\new
CPU-master\MCPU\MCPU.srcs\sim_1\new\BasysSim.sv
CPU-master\MCPU\MCPU.srcs\sim_1\new\SIM.sv
CPU-master\MCPU\MCPU.srcs\sources_1
CPU-master\MCPU\MCPU.srcs\sources_1\new
CPU-master\MCPU\MCPU.srcs\sources_1\new\ALU.sv
CPU-master\MCPU\MCPU.srcs\sources_1\new\Adder.sv
CPU-master\MCPU\MCPU.srcs\sources_1\new\Basys.sv
CPU-master\MCPU\MCPU.srcs\sources_1\new\CtrUnit.sv
CPU-master\MCPU\MCPU.srcs\sources_1\new\DataReg.sv
CPU-master\MCPU\MCPU.srcs\sources_1\new\Extender.sv
CPU-master\MCPU\MCPU.srcs\sources_1\new\IR.sv
CPU-master\MCPU\MCPU.srcs\sources_1\new\InsReg.sv
CPU-master\MCPU\MCPU.srcs\sources_1\new\Inst.mem
CPU-master\MCPU\MCPU.srcs\sources_1\new\MCPU.sv
CPU-master\MCPU\MCPU.srcs\sources_1\new\Mux2to1.sv
CPU-master\MCPU\MCPU.srcs\sources_1\new\Mux4to1.sv
CPU-master\MCPU\MCPU.srcs\sources_1\new\NegR.sv
CPU-master\MCPU\MCPU.srcs\sources_1\new\PC.sv
CPU-master\MCPU\MCPU.srcs\sources_1\new\PCprocess.sv
CPU-master\MCPU\MCPU.srcs\sources_1\new\PosR.sv
CPU-master\MCPU\MCPU.srcs\sources_1\new\Register.sv
CPU-master\MCPU\MCPU.srcs\sources_1\new\ShifterL.sv
CPU-master\MCPU\MCPU.srcs\sources_1\new\btnDebounce.sv
CPU-master\MCPU\MCPU.srcs\sources_1\new\clkDiv.sv
CPU-master\MCPU\MCPU.srcs\sources_1\new\display.sv
CPU-master\MCPU\MCPU.xpr
CPU-master\README.md
CPU-master\SCPU
CPU-master\SCPU\CPU.hw
CPU-master\SCPU\CPU.hw\CPU.lpr
CPU-master\SCPU\CPU.hw\webtalk
CPU-master\SCPU\CPU.hw\webtalk\.xsim_webtallk.info
CPU-master\SCPU\CPU.ip_user_files
CPU-master\SCPU\CPU.ip_user_files\README.txt
CPU-master\SCPU\CPU.ip_user_files\mem_init_files
CPU-master\SCPU\CPU.ip_user_files\mem_init_files\Inst.mem
CPU-master\SCPU\CPU.runs
CPU-master\SCPU\CPU.runs\impl_1
CPU-master\SCPU\CPU.runs\impl_1\ISEWrap.js
CPU-master\SCPU\CPU.runs\impl_1\htr.txt
CPU-master\SCPU\CPU.runs\impl_1\rundef.js
CPU-master\SCPU\CPU.runs\synth_1
CPU-master\SCPU\CPU.runs\synth_1\.Xil
CPU-master\SCPU\CPU.runs\synth_1\.Xil\Basys_propImpl.xdc
CPU-master\SCPU\CPU.runs\synth_1\ISEWrap.js
CPU-master\SCPU\CPU.runs\synth_1\htr.txt
CPU-master\SCPU\CPU.runs\synth_1\rundef.js
CPU-master\SCPU\CPU.sim
CPU-master\SCPU\CPU.sim\sim_1
CPU-master\SCPU\CPU.sim\sim_1\behav
CPU-master\SCPU\CPU.sim\sim_1\behav\Inst.mem
CPU-master\SCPU\CPU.sim\sim_1\behav\SIM_vlog.prj
CPU-master\SCPU\CPU.sim\sim_1\behav\xsim.dir
CPU-master\SCPU\CPU.sim\sim_1\behav\xsim.dir\SIM_behav
CPU-master\SCPU\CPU.sim\sim_1\behav\xsim.dir\SIM_behav\Compile_Options.txt
CPU-master\SCPU\CPU.sim\sim_1\behav\xsim.dir\SIM_behav\TempBreakPointFile.txt
CPU-master\SCPU\CPU.sim\sim_1\behav\xsim.dir\SIM_behav\webtalk
CPU-master\SCPU\CPU.sim\sim_1\behav\xsim.dir\SIM_behav\webtalk\.xsim_webtallk.info
CPU-master\SCPU\CPU.sim\sim_1\behav\xsim.dir\SIM_behav\xsimSettings.ini
CPU-master\SCPU\CPU.sim\sim_1\behav\xsim.ini
CPU-master\SCPU\CPU.sim\sim_1\synth
CPU-master\SCPU\CPU.sim\sim_1\synth\func
CPU-master\SCPU\CPU.sim\sim_1\synth\func\Inst.mem
CPU-master\SCPU\CPU.sim\sim_1\synth\func\SIM_vlog.prj
CPU-master\SCPU\CPU.sim\sim_1\synth\func\xsim.dir
CPU-master\SCPU\CPU.sim\sim_1\synth\func\xsim.dir\SIM_func_synth
CPU-master\SCPU\CPU.sim\sim_1\synth\func\xsim.dir\SIM_func_synth\webtalk
CPU-master\SCPU\CPU.sim\sim_1\synth\func\xsim.dir\SIM_func_synth\webtalk\.xsim_webtallk.info
CPU-master\SCPU\CPU.sim\sim_1\synth\func\xsim.dir\SIM_func_synth\xsimSettings.ini
CPU-master\SCPU\CPU.sim\sim_1\synth\func\xsim.ini

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