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文件名称:DDR3

  • 所属分类：
    VHDL/FPGA/Verilog
  • 标签属性：
    [PDF]
  • 上传时间：
    2017-11-09
  • 文件大小：
    27.74mb
  • 已下载：
    0次
  • 提 供 者：
    时光***
  • 相关连接：
    无
  • 下载说明：
    别用迅雷下载，失败请重下，重下不扣分！
修正介绍说明

介绍说明－－下载内容来自于网络，使用问题请自行百度

spartan6 里使用DDR3IP核，有教程以及源码(spartan6　with ddr3,source and tutorial)
相关搜索： Spartan6 DDR3

(系统自动生成,下载前可以参看下载内容)

下载文件列表

MiS603 FPGA开发教程V1.4_hdl.pdf
CH15_DDR_TEST\MIG_PRG\DOC\SPARTAN6 MCB MIG Core生成.doc
CH15_DDR_TEST\MIG_PRG\DOC\ug388.pdf
CH15_DDR_TEST\MIG_PRG\DOC\ug416.pdf
CH15_DDR_TEST\MIG_PRG\MIG_RPG\mig.prj
CH15_DDR_TEST\MIG_PRG\MIG_RPG\mis603\docs\ug388.pdf
CH15_DDR_TEST\MIG_PRG\MIG_RPG\mis603\docs\ug416.pdf
CH15_DDR_TEST\MIG_PRG\MIG_RPG\mis603\example_design\datasheet.txt
CH15_DDR_TEST\MIG_PRG\MIG_RPG\mis603\example_design\log.txt
CH15_DDR_TEST\MIG_PRG\MIG_RPG\mis603\example_design\mig.prj
CH15_DDR_TEST\MIG_PRG\MIG_RPG\mis603\example_design\par\create_ise.bat
CH15_DDR_TEST\MIG_PRG\MIG_RPG\mis603\example_design\par\example_top.ucf
CH15_DDR_TEST\MIG_PRG\MIG_RPG\mis603\example_design\par\icon_coregen.xco
CH15_DDR_TEST\MIG_PRG\MIG_RPG\mis603\example_design\par\ila_coregen.xco
CH15_DDR_TEST\MIG_PRG\MIG_RPG\mis603\example_design\par\ise_flow.bat
CH15_DDR_TEST\MIG_PRG\MIG_RPG\mis603\example_design\par\ise_run.txt
CH15_DDR_TEST\MIG_PRG\MIG_RPG\mis603\example_design\par\makeproj.bat
CH15_DDR_TEST\MIG_PRG\MIG_RPG\mis603\example_design\par\mem_interface_top.ut
CH15_DDR_TEST\MIG_PRG\MIG_RPG\mis603\example_design\par\readme.txt
CH15_DDR_TEST\MIG_PRG\MIG_RPG\mis603\example_design\par\rem_files.bat
CH15_DDR_TEST\MIG_PRG\MIG_RPG\mis603\example_design\par\set_ise_prop.tcl
CH15_DDR_TEST\MIG_PRG\MIG_RPG\mis603\example_design\par\vio_coregen.xco
CH15_DDR_TEST\MIG_PRG\MIG_RPG\mis603\example_design\rtl\example_top.v
CH15_DDR_TEST\MIG_PRG\MIG_RPG\mis603\example_design\rtl\infrastructure.v
CH15_DDR_TEST\MIG_PRG\MIG_RPG\mis603\example_design\rtl\mcb_controller\iodrp_controller.v
CH15_DDR_TEST\MIG_PRG\MIG_RPG\mis603\example_design\rtl\mcb_controller\iodrp_mcb_controller.v
CH15_DDR_TEST\MIG_PRG\MIG_RPG\mis603\example_design\rtl\mcb_controller\mcb_raw_wrapper.v
CH15_DDR_TEST\MIG_PRG\MIG_RPG\mis603\example_design\rtl\mcb_controller\mcb_soft_calibration.v
CH15_DDR_TEST\MIG_PRG\MIG_RPG\mis603\example_design\rtl\mcb_controller\mcb_soft_calibration_top.v
CH15_DDR_TEST\MIG_PRG\MIG_RPG\mis603\example_design\rtl\mcb_controller\mcb_ui_top.v
CH15_DDR_TEST\MIG_PRG\MIG_RPG\mis603\example_design\rtl\memc_tb_top.v
CH15_DDR_TEST\MIG_PRG\MIG_RPG\mis603\example_design\rtl\memc_wrapper.v
CH15_DDR_TEST\MIG_PRG\MIG_RPG\mis603\example_design\rtl\traffic_gen\afifo.v
CH15_DDR_TEST\MIG_PRG\MIG_RPG\mis603\example_design\rtl\traffic_gen\cmd_gen.v
CH15_DDR_TEST\MIG_PRG\MIG_RPG\mis603\example_design\rtl\traffic_gen\cmd_prbs_gen.v
CH15_DDR_TEST\MIG_PRG\MIG_RPG\mis603\example_design\rtl\traffic_gen\data_prbs_gen.v
CH15_DDR_TEST\MIG_PRG\MIG_RPG\mis603\example_design\rtl\traffic_gen\init_mem_pattern_ctr.v
CH15_DDR_TEST\MIG_PRG\MIG_RPG\mis603\example_design\rtl\traffic_gen\mcb_flow_control.v
CH15_DDR_TEST\MIG_PRG\MIG_RPG\mis603\example_design\rtl\traffic_gen\mcb_traffic_gen.v
CH15_DDR_TEST\MIG_PRG\MIG_RPG\mis603\example_design\rtl\traffic_gen\rd_data_gen.v
CH15_DDR_TEST\MIG_PRG\MIG_RPG\mis603\example_design\rtl\traffic_gen\read_data_path.v
CH15_DDR_TEST\MIG_PRG\MIG_RPG\mis603\example_design\rtl\traffic_gen\read_posted_fifo.v
CH15_DDR_TEST\MIG_PRG\MIG_RPG\mis603\example_design\rtl\traffic_gen\sp6_data_gen.v
CH15_DDR_TEST\MIG_PRG\MIG_RPG\mis603\example_design\rtl\traffic_gen\tg_status.v
CH15_DDR_TEST\MIG_PRG\MIG_RPG\mis603\example_design\rtl\traffic_gen\v6_data_gen.v
CH15_DDR_TEST\MIG_PRG\MIG_RPG\mis603\example_design\rtl\traffic_gen\write_data_path.v
CH15_DDR_TEST\MIG_PRG\MIG_RPG\mis603\example_design\rtl\traffic_gen\wr_data_gen.v
CH15_DDR_TEST\MIG_PRG\MIG_RPG\mis603\example_design\sim\functional\ddr3_model_c3.v
CH15_DDR_TEST\MIG_PRG\MIG_RPG\mis603\example_design\sim\functional\ddr3_model_parameters_c3.vh
CH15_DDR_TEST\MIG_PRG\MIG_RPG\mis603\example_design\sim\functional\isim.bat
CH15_DDR_TEST\MIG_PRG\MIG_RPG\mis603\example_design\sim\functional\isim.tcl
CH15_DDR_TEST\MIG_PRG\MIG_RPG\mis603\example_design\sim\functional\mis603.prj
CH15_DDR_TEST\MIG_PRG\MIG_RPG\mis603\example_design\sim\functional\readme.txt
CH15_DDR_TEST\MIG_PRG\MIG_RPG\mis603\example_design\sim\functional\sim.do
CH15_DDR_TEST\MIG_PRG\MIG_RPG\mis603\example_design\sim\functional\sim_tb_top.v
CH15_DDR_TEST\MIG_PRG\MIG_RPG\mis603\example_design\synth\example_top.lso
CH15_DDR_TEST\MIG_PRG\MIG_RPG\mis603\example_design\synth\example_top.prj
CH15_DDR_TEST\MIG_PRG\MIG_RPG\mis603\example_design\synth\mem_interface_top_synp.sdc
CH15_DDR_TEST\MIG_PRG\MIG_RPG\mis603\example_design\synth\script_synp.tcl
CH15_DDR_TEST\MIG_PRG\MIG_RPG\mis603\user_design\datasheet.txt
CH15_DDR_TEST\MIG_PRG\MIG_RPG\mis603\user_design\log.txt
CH15_DDR_TEST\MIG_PRG\MIG_RPG\mis603\user_design\mig.prj
CH15_DDR_TEST\MIG_PRG\MIG_RPG\mis603\user_design\par\create_ise.bat
CH15_DDR_TEST\MIG_PRG\MIG_RPG\mis603\user_design\par\icon_coregen.xco
CH15_DDR_TEST\MIG_PRG\MIG_RPG\mis603\user_design\par\ila_coregen.xco
CH15_DDR_TEST\MIG_PRG\MIG_RPG\mis603\user_design\par\ise_flow.bat
CH15_DDR_TEST\MIG_PRG\MIG_RPG\mis603\user_design\par\ise_run.txt
CH15_DDR_TEST\MIG_PRG\MIG_RPG\mis603\user_design\par\makeproj.bat
CH15_DDR_TEST\MIG_PRG\MIG_RPG\mis603\user_design\par\mem_interface_top.ut
CH15_DDR_TEST\MIG_PRG\MIG_RPG\mis603\user_design\par\mis603.ucf
CH15_DDR_TEST\MIG_PRG\MIG_RPG\mis603\user_design\par\readme.txt
CH15_DDR_TEST\MIG_PRG\MIG_RPG\mis603\user_design\par\rem_files.bat
CH15_DDR_TEST\MIG_PRG\MIG_RPG\mis603\user_design\par\set_ise_prop.tcl
CH15_DDR_TEST\MIG_PRG\MIG_RPG\mis603\user_design\par\vio_coregen.xco
CH15_DDR_TEST\MIG_PRG\MIG_RPG\mis603\user_design\rtl\infrastructure.v
CH15_DDR_TEST\MIG_PRG\MIG_RPG\mis603\user_design\rtl\mcb_controller\iodrp_controller.v
CH15_DDR_TEST\MIG_PRG\MIG_RPG\mis603\user_design\rtl\mcb_controller\iodrp_mcb_controller.v
CH15_DDR_TEST\MIG_PRG\MIG_RPG\mis603\user_design\rtl\mcb_controller\mcb_raw_wrapper.v
CH15_DDR_TEST\MIG_PRG\MIG_RPG\mis603\user_design\rtl\mcb_controller\mcb_soft_calibration.v
CH15_DDR_TEST\MIG_PRG\MIG_RPG\mis603\user_design\rtl\mcb_controller\mcb_soft_calibration_top.v
CH15_DDR_TEST\MIG_PRG\MIG_RPG\mis603\user_design\rtl\mcb_controller\mcb_ui_top.v
CH15_DDR_TEST\MIG_PRG\MIG_RPG\mis603\user_design\rtl\memc_wrapper.v
CH15_DDR_TEST\MIG_PRG\MIG_RPG\mis603\user_design\rtl\mis603.v
CH15_DDR_TEST\MIG_PRG\MIG_RPG\mis603\user_design\sim\afifo.v
CH15_DDR_TEST\MIG_PRG\MIG_RPG\mis603\user_design\sim\cmd_gen.v
CH15_DDR_TEST\MIG_PRG\MIG_RPG\mis603\user_design\sim\cmd_prbs_gen.v
CH15_DDR_TEST\MIG_PRG\MIG_RPG\mis603\user_design\sim\data_prbs_gen.v
CH15_DDR_TEST\MIG_PRG\MIG_RPG\mis603\user_design\sim\ddr3_model_c3.v
CH15_DDR_TEST\MIG_PRG\MIG_RPG\mis603\user_design\sim\ddr3_model_parameters_c3.vh
CH15_DDR_TEST\MIG_PRG\MIG_RPG\mis603\user_design\sim\init_mem_pattern_ctr.v
CH15_DDR_TEST\MIG_PRG\MIG_RPG\mis603\user_design\sim\isim.bat
CH15_DDR_TEST\MIG_PRG\MIG_RPG\mis603\user_design\sim\isim.tcl
CH15_DDR_TEST\MIG_PRG\MIG_RPG\mis603\user_design\sim\mcb_flow_control.v
CH15_DDR_TEST\MIG_PRG\MIG_RPG\mis603\user_design\sim\mcb_traffic_gen.v
CH15_DDR_TEST\MIG_PRG\MIG_RPG\mis603\user_design\sim\memc_tb_top.v
CH15_DDR_TEST\MIG_PRG\MIG_RPG\mis603\user_design\sim\mis603.prj
CH15_DDR_TEST\MIG_PRG\MIG_RPG\mis603\user_design\sim\rd_data_gen.v
CH15_DDR_TEST\MIG_PRG\MIG_RPG\mis603\user_design\sim\readme.txt
CH15_DDR_TEST\MIG_PRG\MIG_RPG\mis603\user_design\sim\read_data_path.v
CH15_DDR_TEST\MIG_PRG\MIG_RPG\mis603\user_design\sim\read_posted_fifo.v

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