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文件名称:eetop.cn_i2c_slave

  • 所属分类：
    VHDL/FPGA/Verilog
  • 标签属性：
    [ASM] [源码]
  • 上传时间：
    2017-11-24
  • 文件大小：
    290kb
  • 已下载：
    0次
  • 提 供 者：
    jacke*****
  • 相关连接：
    无
  • 下载说明：
    别用迅雷下载，失败请重下，重下不扣分！
修正介绍说明

介绍说明－－下载内容来自于网络，使用问题请自行百度

verilog 编写的i2c代码，很好，很清晰(i2c coding wrote by verilog)
相关搜索： i2c

(系统自动生成,下载前可以参看下载内容)

下载文件列表

文件名大小更新时间
I2C\design\I2CSlave.prd 264 2006-11-15
I2C\design\I2CSlave.prj 1331 2006-11-15
I2C\design\I2Cslave.v 9373 2006-11-16
I2C\design\myram.v 386 2006-11-16
I2C\design\rev_1\.recordref
I2C\design\rev_1\AutoConstraint_I2Cslave.sdc 176 2006-11-15
I2C\design\rev_1\AutoConstraint_myRAM.sdc 173 2006-11-15
I2C\design\rev_1\I2Cslave.edf 66940 2006-11-15
I2C\design\rev_1\I2Cslave.fse 503 2006-11-15
I2C\design\rev_1\I2Cslave.htm 336 2006-11-15
I2C\design\rev_1\I2Cslave.ncf 459 2006-11-15
I2C\design\rev_1\I2Cslave.srd 32388 2006-11-15
I2C\design\rev_1\I2Cslave.srm 60654 2006-11-15
I2C\design\rev_1\I2Cslave.srr 21557 2006-11-15
I2C\design\rev_1\I2Cslave.srs 11157 2006-11-15
I2C\design\rev_1\I2Cslave.tlg 380 2006-11-15
I2C\design\rev_1\myram.edf 17437 2006-11-15
I2C\design\rev_1\myram.fse
I2C\design\rev_1\myram.htm 324 2006-11-15
I2C\design\rev_1\myram.ncf 591 2006-11-15
I2C\design\rev_1\myram.srd 7490 2006-11-15
I2C\design\rev_1\myram.srm 15942 2006-11-15
I2C\design\rev_1\myram.srr 14253 2006-11-15
I2C\design\rev_1\myram.srs 2265 2006-11-15
I2C\design\rev_1\myram.tlg 187 2006-11-15
I2C\design\rev_1\rpt_I2Cslave.areasrr 2100 2006-11-15
I2C\design\rev_1\rpt_I2Cslave_areasrr.htm 2545 2006-11-15
I2C\design\rev_1\rpt_myRAM.areasrr 2076 2006-11-15
I2C\design\rev_1\rpt_myRAM_areasrr.htm 2509 2006-11-15
I2C\design\rev_1\rpt_slave_top.areasrr 2105 2006-11-13
I2C\design\rev_1\rpt_slave_top_areasrr.htm 2554 2006-11-13
I2C\design\rev_1\slave_top.edf 1117 2006-11-13
I2C\design\rev_1\slave_top.fse
I2C\design\rev_1\slave_top.htm 340 2006-11-15
I2C\design\rev_1\slave_top.ncf 246 2006-11-13
I2C\design\rev_1\slave_top.srd 1215 2006-11-13
I2C\design\rev_1\slave_top.srm 1257 2006-11-13
I2C\design\rev_1\slave_top.srr 4532 2006-11-13
I2C\design\rev_1\slave_top.srs 2086 2006-11-13
I2C\design\rev_1\slave_top.tlg 1491 2006-11-13
I2C\design\rev_1\syntmp\I2Cslave.msg 830 2006-11-15
I2C\design\rev_1\syntmp\I2Cslave.plg 493 2006-11-15
I2C\design\rev_1\syntmp\I2Cslave_flink.htm 795 2006-11-15
I2C\design\rev_1\syntmp\I2Cslave_srr.htm 23483 2006-11-15
I2C\design\rev_1\syntmp\I2Cslave_toc.htm 1395 2006-11-15
I2C\design\rev_1\syntmp\myram.msg 970 2006-11-15
I2C\design\rev_1\syntmp\myram.plg 505 2006-11-15
I2C\design\rev_1\syntmp\myram_flink.htm 795 2006-11-15
I2C\design\rev_1\syntmp\myram_srr.htm 15295 2006-11-15
I2C\design\rev_1\syntmp\myram_toc.htm 1349 2006-11-15
I2C\design\rev_1\syntmp\slave_top.msg
I2C\design\rev_1\syntmp\slave_top.plg 208 2006-11-13
I2C\design\rev_1\syntmp\slave_top_flink.htm 507 2006-11-15
I2C\design\rev_1\syntmp\slave_top_srr.htm 6946 2006-11-15
I2C\design\rev_1\syntmp\slave_top_toc.htm 855 2006-11-15
I2C\design\rev_1\syntmp\timescale_flink.htm 358 2006-11-13
I2C\design\rev_1\syntmp\timescale_srr.htm 711 2006-11-13
I2C\design\rev_1\syntmp\timescale_toc.htm 439 2006-11-13
I2C\design\rev_1\syntmp
I2C\design\rev_1\timescale.htm 340 2006-11-13
I2C\design\rev_1\timescale.srr 579 2006-11-13
I2C\design\rev_1\traplog.tlg 1951 2006-11-15
I2C\design\rev_1\verif\I2Cslave.vif 2292 2006-11-15
I2C\design\rev_1\verif\myram.vif 1299 2006-11-15
I2C\design\rev_1\verif\slave_top.vif 1408 2006-11-13
I2C\design\rev_1\verif
I2C\design\rev_1
I2C\design\sim\all.do 3132 2006-11-15
I2C\design\sim\i2c_master_bit_ctrl.v 17487 2006-09-04
I2C\design\sim\i2c_master_byte_ctrl.v 10547 2004-02-18
I2C\design\sim\i2c_master_defines.v 3219 2001-11-05
I2C\design\sim\i2c_master_top.v 10108 2005-02-27
I2C\design\sim\Sim_Behav.bat 274 2006-11-14
I2C\design\sim\timescale.v 22 2006-11-14
I2C\design\sim\transcript 2349 2006-11-28
I2C\design\sim\tst_bench_top.v 15120 2006-11-16
I2C\design\sim\vish_stacktrace.vstf 7108 2006-11-16
I2C\design\sim\vsim.wlf 81920 2006-11-16
I2C\design\sim\wb_master_model.v 5630 2006-11-10
I2C\design\sim\work\@i2@cslave\verilog.asm 35208 2006-11-28
I2C\design\sim\work\@i2@cslave\_primary.dat 4390 2006-11-28
I2C\design\sim\work\@i2@cslave\_primary.vhd 876 2006-11-28
I2C\design\sim\work\@i2@cslave
I2C\design\sim\work\i2c_master_bit_ctrl\verilog.asm 33948 2006-11-28
I2C\design\sim\work\i2c_master_bit_ctrl\_primary.dat 7011 2006-11-28
I2C\design\sim\work\i2c_master_bit_ctrl\_primary.vhd 1656 2006-11-28
I2C\design\sim\work\i2c_master_bit_ctrl
I2C\design\sim\work\i2c_master_byte_ctrl\verilog.asm 23764 2006-11-28
I2C\design\sim\work\i2c_master_byte_ctrl\_primary.dat 4142 2006-11-28
I2C\design\sim\work\i2c_master_byte_ctrl\_primary.vhd 1380 2006-11-28
I2C\design\sim\work\i2c_master_byte_ctrl
I2C\design\sim\work\i2c_master_top\verilog.asm 26655 2006-11-28
I2C\design\sim\work\i2c_master_top\_primary.dat 3926 2006-11-28
I2C\design\sim\work\i2c_master_top\_primary.vhd 951 2006-11-28
I2C\design\sim\work\i2c_master_top
I2C\design\sim\work\my@r@a@m\verilog.asm 4637 2006-11-28
I2C\design\sim\work\my@r@a@m\_primary.dat 522 2006-11-28
I2C\design\sim\work\my@r@a@m\_primary.vhd 401 2006-11-28
I2C\design\sim\work\my@r@a@m
I2C\design\sim\work\tst_bench_top\verilog.asm 124235 2006-11-28

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