We present an efficient hardware architecture design & implementation of Advanced Encryption Standard AES Rijndael cryptosystem. The AES algorithm defined by the National Institute of Standard and Technology NIST of United States has been widely accepted. All the cryptographic algorithms developed can be implemented with software or built with pure hardware. However with the help of Field Programmable Gate Arrays FPGA we tend to find expeditious solution and which can be easily upgraded to integrateany concordat changes. This contribution investigates the AES encryption and decryption cryptosystem with regard to FPGA and Very High Speed Integrated Circuit Hardware Descr iption language VHDL. Optimized and Synthesizable VHDL code is developed for the implementation of both 128-bit data encryption and decryption process.