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文件名称:Design

  • 所属分类：
    其他
  • 标签属性：
    [C/C++] [源码]
  • 上传时间：
    2018-01-07
  • 文件大小：
    2.88mb
  • 已下载：
    0次
  • 提 供 者：
    jiangn*******
  • 相关连接：
    无
  • 下载说明：
    别用迅雷下载，失败请重下，重下不扣分！
修正介绍说明

介绍说明－－下载内容来自于网络，使用问题请自行百度

利用Xilinx ISE用Verilog编写的计算器(Using Xilinx ISEalculator and register heap program written in Verilog HDL language)
相关搜索： Using Xilinx ISE14.3

(系统自动生成,下载前可以参看下载内容)

下载文件列表

文件名大小更新时间
Design\adder_sch.vf 1678 2017-11-24
Design\AddSup1b_drc.vf 1398 2017-11-30
Design\AddSup4b_drc.vf 2732 2018-01-02
Design\AddSup4b_isim_beh.exe 94720 2018-01-01
Design\AddSup4b_stx_beh.prj 267 2018-01-02
Design\AddSup4b_summary.html 3687 2018-01-02
Design\AddSup8b_isim_beh.exe 94720 2018-01-02
Design\clkdiv.v 702 2017-11-20
Design\design.bgn 8142 2018-01-06
Design\design.bit 6692664 2018-01-06
Design\Design.bld 1001 2018-01-06
Design\Design.cmd_log 6433 2018-01-06
Design\design.drc 190 2018-01-06
Design\Design.gise 20731 2018-01-06
Design\Design.lso 6 2018-01-06
Design\Design.ncd 43986 2018-01-06
Design\Design.ngc 44414 2018-01-06
Design\Design.ngd 68098 2018-01-06
Design\Design.ngr 49015 2018-01-06
Design\Design.pad 28956 2018-01-06
Design\Design.par 8692 2018-01-06
Design\Design.pcf 1325 2018-01-06
Design\Design.prj 171 2018-01-06
Design\Design.ptwx 17233 2018-01-06
Design\Design.stx 0 2018-01-06
Design\Design.syr 24168 2018-01-06
Design\Design.twr 5095 2018-01-06
Design\Design.twx 23189 2018-01-06
Design\Design.unroutes 161 2018-01-06
Design\Design.ut 742 2018-01-06
Design\Design.v 2568 2018-01-05
Design\Design.xise 38175 2018-01-05
Design\Design.xpi 46 2018-01-06
Design\Design.xst 1068 2018-01-06
Design\Design_bitgen.xwbt 197 2018-01-06
Design\Design_envsettings.html 10792 2018-01-06
Design\Design_guide.ncd 43986 2018-01-06
Design\Design_isim_beh.exe 94720 2018-01-02
Design\Design_map.map 7353 2018-01-06
Design\Design_map.mrp 16150 2018-01-06
Design\Design_map.ncd 23270 2018-01-06
Design\Design_map.ngm 120130 2018-01-06
Design\Design_map.xrpt 28988 2018-01-06
Design\Design_ngdbuild.xrpt 6704 2018-01-06
Design\Design_pad.csv 28989 2018-01-06
Design\Design_pad.txt 133038 2018-01-06
Design\Design_par.xrpt 293034 2018-01-06
Design\Design_stx_beh.prj 98 2018-01-02
Design\Design_summary.html 17663 2018-01-06
Design\Design_summary.xml 409 2018-01-06
Design\Design_usage.xml 15842 2018-01-06
Design\Design_xst.xrpt 13517 2018-01-06
Design\D_en_drc.vf 1586 2017-12-22
Design\D_latch.vf 1597 2017-12-07
Design\fuse.log 2089 2018-01-05
Design\fuse.xmsgs 1021 2018-01-05
Design\fuseRelaunch.cmd 222 2018-01-05
Design\iseconfig\AddSup4b.xreport 20452 2018-01-02
Design\iseconfig\Design.projectmgr 9658 2018-01-06
Design\iseconfig\Design.xreport 20462 2018-01-06
Design\isim\isim_usage_statistics.html 1682 2018-01-05
Design\isim\pn_info 6 2018-01-05
Design\isim\work\@design.sdb 8867 2018-01-05
Design\isim\work\@mux4to1b4.sdb 9848 2018-01-05
Design\isim\work\@my@m@c14495.sdb 14015 2018-01-05
Design\isim\work\clkdiv.sdb 1228 2018-01-05
Design\isim\work\glbl.sdb 4718 2018-01-05
Design\isim\work\pbdebounce.sdb 1632 2018-01-05
Design\isim\work\scordboard.sdb 4946 2018-01-05
Design\isim\work\yyeest.sdb 4711 2018-01-05
Design\isim\yyeest_isim_beh.exe.sim\isimcrash.log 0 2018-01-05
Design\isim\yyeest_isim_beh.exe.sim\ISimEngine-DesignHierarchy.dbg 48901 2018-01-05
Design\isim\yyeest_isim_beh.exe.sim\isimkernel.log 570 2018-01-05
Design\isim\yyeest_isim_beh.exe.sim\netId.dat 84 2018-01-05
Design\isim\yyeest_isim_beh.exe.sim\tmp_save\_1 27146 2018-01-05
Design\isim\yyeest_isim_beh.exe.sim\unisims_ver\m_00000000000236260522_2449448540.c 1984 2018-01-05
Design\isim\yyeest_isim_beh.exe.sim\unisims_ver\m_00000000000236260522_2449448540.didat 2276 2018-01-05
Design\isim\yyeest_isim_beh.exe.sim\unisims_ver\m_00000000000236260522_2449448540.nt64.obj 1117 2018-01-05
Design\isim\yyeest_isim_beh.exe.sim\unisims_ver\m_00000000001162476414_1323117156.c 2130 2018-01-05
Design\isim\yyeest_isim_beh.exe.sim\unisims_ver\m_00000000001162476414_1323117156.didat 2476 2018-01-05
Design\isim\yyeest_isim_beh.exe.sim\unisims_ver\m_00000000001162476414_1323117156.nt64.obj 1132 2018-01-05
Design\isim\yyeest_isim_beh.exe.sim\unisims_ver\m_00000000001762375489_3501834183.c 2202 2018-01-05
Design\isim\yyeest_isim_beh.exe.sim\unisims_ver\m_00000000001762375489_3501834183.didat 2576 2018-01-05
Design\isim\yyeest_isim_beh.exe.sim\unisims_ver\m_00000000001762375489_3501834183.nt64.obj 1148 2018-01-05
Design\isim\yyeest_isim_beh.exe.sim\unisims_ver\m_00000000002123152668_0970595058.c 2058 2018-01-05
Design\isim\yyeest_isim_beh.exe.sim\unisims_ver\m_00000000002123152668_0970595058.didat 2376 2018-01-05
Design\isim\yyeest_isim_beh.exe.sim\unisims_ver\m_00000000002123152668_0970595058.nt64.obj 1116 2018-01-05
Design\isim\yyeest_isim_beh.exe.sim\unisims_ver\m_00000000002549801008_4245414866.c 2131 2018-01-05
Design\isim\yyeest_isim_beh.exe.sim\unisims_ver\m_00000000002549801008_4245414866.didat 2480 2018-01-05
Design\isim\yyeest_isim_beh.exe.sim\unisims_ver\m_00000000002549801008_4245414866.nt64.obj 1133 2018-01-05
Design\isim\yyeest_isim_beh.exe.sim\unisims_ver\m_00000000003149700083_1668249201.c 2203 2018-01-05
Design\isim\yyeest_isim_beh.exe.sim\unisims_ver\m_00000000003149700083_1668249201.didat 2580 2018-01-05
Design\isim\yyeest_isim_beh.exe.sim\unisims_ver\m_00000000003149700083_1668249201.nt64.obj 1149 2018-01-05
Design\isim\yyeest_isim_beh.exe.sim\unisims_ver\m_00000000003317509437_1759035934.c 2397 2018-01-05
Design\isim\yyeest_isim_beh.exe.sim\unisims_ver\m_00000000003317509437_1759035934.didat 2248 2018-01-05
Design\isim\yyeest_isim_beh.exe.sim\unisims_ver\m_00000000003317509437_1759035934.nt64.obj 1087 2018-01-05
Design\isim\yyeest_isim_beh.exe.sim\unisims_ver\m_00000000003510477262_2316096324.c 2059 2018-01-05
Design\isim\yyeest_isim_beh.exe.sim\unisims_ver\m_00000000003510477262_2316096324.didat 2380 2018-01-05
Design\isim\yyeest_isim_beh.exe.sim\unisims_ver\m_00000000003510477262_2316096324.nt64.obj 1117 2018-01-05
Design\isim\yyeest_isim_beh.exe.sim\unisims_ver\m_00000000003927721830_1593237687.c 2397 2018-01-05

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