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文件名称:DDR2_Control

  • 所属分类：
    其他
  • 标签属性：
    [PDF]
  • 上传时间：
    2018-01-28
  • 文件大小：
    12.44mb
  • 已下载：
    0次
  • 提 供 者：
    chenpeiw********
  • 相关连接：
    无
  • 下载说明：
    别用迅雷下载，失败请重下，重下不扣分！
修正介绍说明

介绍说明－－下载内容来自于网络，使用问题请自行百度

本人用verilog编写的DDR2控制器，经测试可用。(I am prepared to use verilog DDR2 controller, the test is available.)
相关搜索： DDR2 control

(系统自动生成,下载前可以参看下载内容)

下载文件列表

文件名大小更新时间
DDR2_Control 0 2017-11-17
DDR2_Control\Chipscope 0 2015-12-08
DDR2_Control\Chipscope\siga-s16.cpj 101183 2012-12-03
DDR2_Control\Siga_DDR2_MIG_Design.cgc 68416 2012-11-30
DDR2_Control\Siga_DDR2_MIG_Design.cgp 522 2012-11-30
DDR2_Control\_xmsgs 0 2015-12-08
DDR2_Control\_xmsgs\pn_parser.xmsgs 2690 2017-11-17
DDR2_Control\iseconfig 0 2015-12-08
DDR2_Control\iseconfig\mig_37.projectmgr 4415 2017-11-17
DDR2_Control\iseconfig\mig_37.xreport 20841 2017-11-17
DDR2_Control\mig_37 0 2015-12-08
DDR2_Control\mig_37\docs 0 2015-12-08
DDR2_Control\mig_37\docs\ug388.pdf 2172724 2010-10-06
DDR2_Control\mig_37\docs\ug416.pdf 7337767 2010-10-06
DDR2_Control\mig_37\example_design 0 2015-12-08
DDR2_Control\mig_37\example_design\datasheet.txt 2359 2012-11-30
DDR2_Control\mig_37\example_design\log.txt 2594 2012-11-30
DDR2_Control\mig_37\example_design\mig.prj 2958 2012-11-30
DDR2_Control\mig_37\example_design\par 0 2015-12-08
DDR2_Control\mig_37\example_design\par\_ngo 0 2015-12-08
DDR2_Control\mig_37\example_design\par\_ngo\netlist.lst 341 2012-12-07
DDR2_Control\mig_37\example_design\par\_xmsgs 0 2015-12-08
DDR2_Control\mig_37\example_design\par\_xmsgs\bitgen.xmsgs 3058 2012-12-07
DDR2_Control\mig_37\example_design\par\_xmsgs\map.xmsgs 4755 2012-12-07
DDR2_Control\mig_37\example_design\par\_xmsgs\ngdbuild.xmsgs 172223 2012-12-07
DDR2_Control\mig_37\example_design\par\_xmsgs\par.xmsgs 3458 2012-12-07
DDR2_Control\mig_37\example_design\par\_xmsgs\pn_parser.xmsgs 6408 2012-12-20
DDR2_Control\mig_37\example_design\par\_xmsgs\trce.xmsgs 905 2012-12-07
DDR2_Control\mig_37\example_design\par\_xmsgs\xst.xmsgs 656734 2012-12-07
DDR2_Control\mig_37\example_design\par\coregen.cgc 63725 2012-11-30
DDR2_Control\mig_37\example_design\par\coregen.cgp 518 2012-11-30
DDR2_Control\mig_37\example_design\par\coregen.log 1651 2012-11-30
DDR2_Control\mig_37\example_design\par\create_ise.bat 3265 2012-11-30
DDR2_Control\mig_37\example_design\par\example_top.bgn 8901 2012-12-07
DDR2_Control\mig_37\example_design\par\example_top.bit 464310 2012-12-07
DDR2_Control\mig_37\example_design\par\example_top.bld 70638 2012-12-07
DDR2_Control\mig_37\example_design\par\example_top.cdc 13980 2012-11-30
DDR2_Control\mig_37\example_design\par\example_top.cmd_log 2150 2012-12-07
DDR2_Control\mig_37\example_design\par\example_top.drc 2375 2012-12-07
DDR2_Control\mig_37\example_design\par\example_top.ncd 989397 2012-12-07
DDR2_Control\mig_37\example_design\par\example_top.ngc 1618655 2012-12-07
DDR2_Control\mig_37\example_design\par\example_top.ngd 2925424 2012-12-07
DDR2_Control\mig_37\example_design\par\example_top.ngr 2379162 2012-12-07
DDR2_Control\mig_37\example_design\par\example_top.pad 15682 2012-12-07
DDR2_Control\mig_37\example_design\par\example_top.par 21762 2012-12-07
DDR2_Control\mig_37\example_design\par\example_top.pcf 479810 2012-12-07
DDR2_Control\mig_37\example_design\par\example_top.prj 1260 2012-12-07
DDR2_Control\mig_37\example_design\par\example_top.ptwx 23122 2012-12-07
DDR2_Control\mig_37\example_design\par\example_top.stx 0 2012-12-07
DDR2_Control\mig_37\example_design\par\example_top.syr 521423 2012-12-07
DDR2_Control\mig_37\example_design\par\example_top.twr 237319 2012-12-07
DDR2_Control\mig_37\example_design\par\example_top.twx 270037 2012-12-07
DDR2_Control\mig_37\example_design\par\example_top.ucf 10567 2012-11-30
DDR2_Control\mig_37\example_design\par\example_top.unroutes 1025 2012-12-07
DDR2_Control\mig_37\example_design\par\example_top.ut 552 2012-12-07
DDR2_Control\mig_37\example_design\par\example_top.xpi 46 2012-12-07
DDR2_Control\mig_37\example_design\par\example_top.xst 1179 2012-12-07
DDR2_Control\mig_37\example_design\par\example_top_bitgen.xwbt 356 2012-12-07
DDR2_Control\mig_37\example_design\par\example_top_envsettings.html 15114 2012-12-20
DDR2_Control\mig_37\example_design\par\example_top_guide.ncd 989397 2012-12-07
DDR2_Control\mig_37\example_design\par\example_top_map.map 10155 2012-12-07
DDR2_Control\mig_37\example_design\par\example_top_map.mrp 60732 2012-12-07
DDR2_Control\mig_37\example_design\par\example_top_map.ncd 527674 2012-12-07
DDR2_Control\mig_37\example_design\par\example_top_map.ngm 5386177 2012-12-07
DDR2_Control\mig_37\example_design\par\example_top_map.xrpt 43444 2012-12-07
DDR2_Control\mig_37\example_design\par\example_top_ngdbuild.xrpt 20300 2012-12-07
DDR2_Control\mig_37\example_design\par\example_top_pad.csv 15714 2012-12-07
DDR2_Control\mig_37\example_design\par\example_top_pad.txt 68977 2012-12-07
DDR2_Control\mig_37\example_design\par\example_top_par.xrpt 182755 2012-12-07
DDR2_Control\mig_37\example_design\par\example_top_summary.html 21045 2012-12-20
DDR2_Control\mig_37\example_design\par\example_top_summary.xml 408 2012-12-07
DDR2_Control\mig_37\example_design\par\example_top_usage.xml 217619 2012-12-07
DDR2_Control\mig_37\example_design\par\example_top_xst.xrpt 21092 2012-12-07
DDR2_Control\mig_37\example_design\par\icon.asy 283 2012-11-30
DDR2_Control\mig_37\example_design\par\icon.gise 1159 2012-11-30
DDR2_Control\mig_37\example_design\par\icon.ngc 40907 2012-11-30
DDR2_Control\mig_37\example_design\par\icon.xco 1380 2012-11-30
DDR2_Control\mig_37\example_design\par\icon.xise 40064 2012-11-30
DDR2_Control\mig_37\example_design\par\icon_coregen.xco 1382 2012-11-30
DDR2_Control\mig_37\example_design\par\icon_flist.txt 135 2012-11-30
DDR2_Control\mig_37\example_design\par\icon_readme.txt 1289 2012-11-30
DDR2_Control\mig_37\example_design\par\icon_xmdf.tcl 2138 2012-11-30
DDR2_Control\mig_37\example_design\par\ila.cdc 11125 2012-11-30
DDR2_Control\mig_37\example_design\par\ila.gise 1054 2012-11-30
DDR2_Control\mig_37\example_design\par\ila.ngc 489191 2012-11-30
DDR2_Control\mig_37\example_design\par\ila.xco 3869 2012-11-30
DDR2_Control\mig_37\example_design\par\ila.xise 40054 2012-11-30
DDR2_Control\mig_37\example_design\par\ila_coregen.xco 3871 2012-11-30
DDR2_Control\mig_37\example_design\par\ila_flist.txt 126 2012-11-30
DDR2_Control\mig_37\example_design\par\ila_readme.txt 1182 2012-11-30
DDR2_Control\mig_37\example_design\par\ila_xmdf.tcl 2131 2012-11-30
DDR2_Control\mig_37\example_design\par\ise_flow.bat 4053 2012-11-30
DDR2_Control\mig_37\example_design\par\ise_run.txt 1278 2012-11-30
DDR2_Control\mig_37\example_design\par\iseconfig 0 2015-12-08
DDR2_Control\mig_37\example_design\par\iseconfig\example_top.xreport 21111 2012-12-20
DDR2_Control\mig_37\example_design\par\iseconfig\test.projectmgr 6317 2012-12-18
DDR2_Control\mig_37\example_design\par\makeproj.bat 28 2012-11-30
DDR2_Control\mig_37\example_design\par\mem_interface_top.ut 385 2012-11-30
DDR2_Control\mig_37\example_design\par\pa.fromNetlist.tcl 689 2012-12-07
DDR2_Control\mig_37\example_design\par\par_usage_statistics.html 4153 2012-12-07

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