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文件名称:AES加密算法密码模块

  • 所属分类：
    VHDL/FPGA/Verilog
  • 标签属性：
    [PDF]
  • 上传时间：
    2018-02-03
  • 文件大小：
    77kb
  • 已下载：
    0次
  • 提 供 者：
    未*****
  • 相关连接：
    无
  • 下载说明：
    别用迅雷下载，失败请重下，重下不扣分！
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其实现了AES加密中的密码模块，包含了功能的说明，模块以及测试用例，学习上手的难度较小(The realization of the AES encryption password module, contains a descr iption of the function modules and test cases, learning difficult to get started)
相关搜索： 加密 verilog

(系统自动生成,下载前可以参看下载内容)

下载文件列表

文件名大小更新时间
aes_core\bench\CVS\Entries 14 2007-10-06
aes_core\bench\CVS\Repository 15 2007-10-06
aes_core\bench\CVS\Root 13 2007-10-06
aes_core\bench\verilog\CVS\Entries 51 2007-10-06
aes_core\bench\verilog\CVS\Repository 23 2007-10-06
aes_core\bench\verilog\CVS\Root 13 2007-10-06
aes_core\bench\verilog\test_bench_top.v 37033 2002-11-13
aes_core\CVS\Entries 104 2007-10-06
aes_core\CVS\Repository 9 2007-10-06
aes_core\CVS\Root 13 2007-10-06
aes_core\doc\aes.pdf 73346 2002-11-13
aes_core\doc\CVS\Entries 45 2007-10-06
aes_core\doc\CVS\Repository 13 2007-10-06
aes_core\doc\CVS\Root 13 2007-10-06
aes_core\rtl\CVS\Entries 14 2007-10-06
aes_core\rtl\CVS\Repository 13 2007-10-06
aes_core\rtl\CVS\Root 13 2007-10-06
aes_core\rtl\verilog\aes_cipher_top.v 10230 2002-11-09
aes_core\rtl\verilog\aes_inv_cipher_top.v 11671 2002-11-09
aes_core\rtl\verilog\aes_inv_sbox.v 8257 2002-11-09
aes_core\rtl\verilog\aes_key_expand_128.v 3914 2002-11-09
aes_core\rtl\verilog\aes_rcon.v 3773 2002-11-09
aes_core\rtl\verilog\aes_sbox.v 8246 2002-11-09
aes_core\rtl\verilog\CVS\Entries 358 2007-10-06
aes_core\rtl\verilog\CVS\Repository 21 2007-10-06
aes_core\rtl\verilog\CVS\Root 13 2007-10-06
aes_core\rtl\verilog\timescale.v 22 2002-11-13
aes_core\sim\CVS\Entries 14 2007-10-06
aes_core\sim\CVS\Repository 13 2007-10-06
aes_core\sim\CVS\Root 13 2007-10-06
aes_core\sim\rtl_sim\bin\CVS\Entries 47 2007-10-06
aes_core\sim\rtl_sim\bin\CVS\Repository 25 2007-10-06
aes_core\sim\rtl_sim\bin\CVS\Root 13 2007-10-06
aes_core\sim\rtl_sim\bin\Makefile 2236 2002-11-09
aes_core\sim\rtl_sim\CVS\Entries 20 2007-10-06
aes_core\sim\rtl_sim\CVS\Repository 21 2007-10-06
aes_core\sim\rtl_sim\CVS\Root 13 2007-10-06
aes_core\sim\rtl_sim\run\CVS\Entries 12 2007-10-06
aes_core\sim\rtl_sim\run\CVS\Repository 25 2007-10-06
aes_core\sim\rtl_sim\run\CVS\Root 13 2007-10-06
aes_core\sim\rtl_sim\run\waves\CVS\Entries 47 2007-10-06
aes_core\sim\rtl_sim\run\waves\CVS\Repository 31 2007-10-06
aes_core\sim\rtl_sim\run\waves\CVS\Root 13 2007-10-06
aes_core\sim\rtl_sim\run\waves\waves.do 5065 2002-11-09
aes_core\syn\bin\comp.dc 4681 2002-11-09
aes_core\syn\bin\CVS\Entries 189 2007-10-06
aes_core\syn\bin\CVS\Repository 17 2007-10-06
aes_core\syn\bin\CVS\Root 13 2007-10-06
aes_core\syn\bin\design_spec.dc 775 2002-11-09
aes_core\syn\bin\lib_spec.dc 1314 2002-11-09
aes_core\syn\bin\read.dc 1882 2002-11-09
aes_core\syn\CVS\Entries 10 2007-10-06
aes_core\syn\CVS\Repository 13 2007-10-06
aes_core\syn\CVS\Root 13 2007-10-06
aes_core\vim_session.vim 5465 2002-11-09
aes_core\sim\rtl_sim\run\waves\CVS 0 2007-11-02
aes_core\sim\rtl_sim\bin\CVS 0 2007-11-02
aes_core\sim\rtl_sim\run\CVS 0 2007-11-02
aes_core\sim\rtl_sim\run\waves 0 2007-11-02
aes_core\bench\verilog\CVS 0 2007-11-02
aes_core\rtl\verilog\CVS 0 2007-11-02
aes_core\sim\rtl_sim\bin 0 2007-11-02
aes_core\sim\rtl_sim\CVS 0 2007-11-02
aes_core\sim\rtl_sim\run 0 2007-11-02
aes_core\syn\bin\CVS 0 2007-11-02
aes_core\bench\CVS 0 2007-11-02
aes_core\bench\verilog 0 2007-11-02
aes_core\doc\CVS 0 2007-11-02
aes_core\rtl\CVS 0 2007-11-02
aes_core\rtl\verilog 0 2007-11-02
aes_core\sim\CVS 0 2007-11-02
aes_core\sim\rtl_sim 0 2007-11-02
aes_core\syn\bin 0 2007-11-02
aes_core\syn\CVS 0 2007-11-02
aes_core\bench 0 2007-11-02
aes_core\CVS 0 2007-11-02
aes_core\doc 0 2007-11-02
aes_core\rtl 0 2007-11-02
aes_core\sim 0 2007-11-02
aes_core\syn 0 2007-11-02
aes_core 0 2007-11-02

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