文件名称:uart_test_Verilog
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- 上传时间：2018-02-08
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文件大小：125kb
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介绍说明－－下载内容来自于网络，使用问题请自行百度
用verilog实现了uart功能的demo工程。工程使用的IDE为“ISE Design Suite 14.7”，使用时可根据自己硬件，修改引脚配置即可。(The demo project of UART function is realized with Verilog. The IDE used in the project is "ISE Design Suite 14.7", which can be used to modify the pin configuration according to its own hardware.)
相关搜索： FPGA verilog
UART
(系统自动生成,下载前可以参看下载内容)
下载文件列表
| 文件名 | 大小 | 更新时间 |
|---|---|---|
| uart_test_Verilog | 0 | 2018-02-08 |
| uart_test_Verilog\_ngo | 0 | 2018-02-08 |
| uart_test_Verilog\_ngo\netlist.lst | 71 | 2018-01-17 |
| uart_test_Verilog\_xmsgs | 0 | 2018-02-08 |
| uart_test_Verilog\_xmsgs\bitgen.xmsgs | 367 | 2018-01-17 |
| uart_test_Verilog\_xmsgs\map.xmsgs | 1585 | 2018-01-17 |
| uart_test_Verilog\_xmsgs\ngdbuild.xmsgs | 367 | 2018-01-17 |
| uart_test_Verilog\_xmsgs\par.xmsgs | 935 | 2018-01-17 |
| uart_test_Verilog\_xmsgs\pn_parser.xmsgs | 1558 | 2018-02-05 |
| uart_test_Verilog\_xmsgs\trce.xmsgs | 1030 | 2018-01-17 |
| uart_test_Verilog\_xmsgs\xst.xmsgs | 5966 | 2018-01-17 |
| uart_test_Verilog\iseconfig | 0 | 2018-02-08 |
| uart_test_Verilog\iseconfig\UART_TEST.projectmgr | 6818 | 2018-02-05 |
| uart_test_Verilog\rtl | 0 | 2018-02-08 |
| uart_test_Verilog\rtl\clkdiv.v | 727 | 2016-02-25 |
| uart_test_Verilog\rtl\clkdiv.v.bak | 644 | 2015-11-04 |
| uart_test_Verilog\rtl\testdata.v | 1636 | 2015-11-04 |
| uart_test_Verilog\rtl\testdata.v.bak | 908 | 2015-11-04 |
| uart_test_Verilog\rtl\uart_test.v | 1816 | 2018-01-31 |
| uart_test_Verilog\rtl\uart_test.v.bak | 341 | 2015-11-04 |
| uart_test_Verilog\rtl\uartctrl.v | 5160 | 2018-02-01 |
| uart_test_Verilog\rtl\uartrx.v | 3935 | 2018-02-01 |
| uart_test_Verilog\rtl\uartrx.v.bak | 3480 | 2015-11-04 |
| uart_test_Verilog\rtl\uarttx.v | 3265 | 2018-02-01 |
| uart_test_Verilog\uart_test.bit | 340698 | 2018-01-17 |
| uart_test_Verilog\uart_test.gise | 13691 | 2018-02-05 |
| uart_test_Verilog\uart_test.mcs | 936773 | 2018-01-17 |
| uart_test_Verilog\uart_test.xise | 37791 | 2015-11-04 |
| uart_test_Verilog\uartrxtx.ucf | 500 | 2015-11-04 |
| uart_test_Verilog\xlnx_auto_0_xdb | 0 | 2018-02-08 |
| uart_test_Verilog\xlnx_auto_0_xdb\cst.xbcd | 1394 | 2018-01-17 |
| uart_test_Verilog\xst | 0 | 2018-02-08 |
| uart_test_Verilog\xst\dump.xst | 0 | 2018-02-08 |
| uart_test_Verilog\xst\dump.xst\uart_test.prj | 0 | 2018-02-08 |
| uart_test_Verilog\xst\projnav.tmp | 0 | 2018-02-08 |
| uart_test_Verilog\xst\work | 0 | 2018-02-08 |
| uart_test_Verilog\xst\work\work.sdbl | 31468 | 2018-01-17 |
| uart_test_Verilog\xst\work\work.sdbx | 129 | 2018-01-17 |
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