8位上下同步计数器　适宜小型练手操作 易于理解(an 8-bit up and down synchronous counter in VHDL with the following
features:
(1) The same ports are used for signals to be inputted and outputted. The ports are
bi-directionally buffered (three-state).
(2) The counter is with an asynchronous reset that assigns a specific initial value
for counting.
(3) The counter is with a synchronous data load control input for a new value of
counting and an enable control input for allowing the up and down counting.
The load control input has a priority over the enable control input. This
implies that when the load operation is in process the counter operation is
prohibited.
(4) Some data types, such as STD_LOGIC, UNSIGNED, SIGNED and INTEGER,
may be used)