文件名称:Receiver_spartn6_v1
-
所属分类：
- 标签属性：
- 上传时间：2018-02-25
-
文件大小：40kb
-
已下载：0次
-
提 供 者：
-
相关连接：无下载说明：别用迅雷下载，失败请重下，重下不扣分！
介绍说明－－下载内容来自于网络，使用问题请自行百度
Implement design of UART receiver in verilog
相关搜索： verilog Uart
Verilog receiver
(系统自动生成,下载前可以参看下载内容)
下载文件列表
| 文件名 | 大小 | 更新时间 |
|---|---|---|
| Receiver_spartn6_v1 | 0 | 2017-04-14 |
| Receiver_spartn6_v1\display_7seg.v | 1306 | 2017-04-05 |
| Receiver_spartn6_v1\rx_data_buffer.v | 299 | 2017-04-06 |
| Receiver_spartn6_v1\rx_sim_moore1.v | 3197 | 2017-04-06 |
| Receiver_spartn6_v1\rx_smpl_pulse.v | 503 | 2017-03-29 |
| Receiver_spartn6_v1\testbench.v | 1511 | 2017-04-03 |
| Receiver_spartn6_v1\top_design.v | 437 | 2017-03-29 |
| Receiver_spartn6_v1\top_rx.v | 550 | 2017-04-06 |
| Receiver_spartn6_v1\uart_rx.cr.mti | 1937 | 2017-04-14 |
| Receiver_spartn6_v1\uart_rx.mpf | 15246 | 2017-04-14 |
| Receiver_spartn6_v1\vsim.wlf | 16384 | 2017-04-06 |
| Receiver_spartn6_v1\work | 0 | 2017-04-14 |
| Receiver_spartn6_v1\work\display7 | 0 | 2017-04-06 |
| Receiver_spartn6_v1\work\display7\verilog.asm | 7098 | 2017-04-14 |
| Receiver_spartn6_v1\work\display7\_primary.dat | 1501 | 2017-04-14 |
| Receiver_spartn6_v1\work\display7\_primary.vhd | 407 | 2017-04-14 |
| Receiver_spartn6_v1\work\rx_buffer | 0 | 2017-04-06 |
| Receiver_spartn6_v1\work\rx_buffer\verilog.asm | 3741 | 2017-04-14 |
| Receiver_spartn6_v1\work\rx_buffer\_primary.dat | 321 | 2017-04-14 |
| Receiver_spartn6_v1\work\rx_buffer\_primary.vhd | 328 | 2017-04-14 |
| Receiver_spartn6_v1\work\rx_sm | 0 | 2017-04-06 |
| Receiver_spartn6_v1\work\rx_smp_pulse | 0 | 2017-04-06 |
| Receiver_spartn6_v1\work\rx_smp_pulse\verilog.asm | 4119 | 2017-04-14 |
| Receiver_spartn6_v1\work\rx_smp_pulse\_primary.dat | 541 | 2017-04-14 |
| Receiver_spartn6_v1\work\rx_smp_pulse\_primary.vhd | 272 | 2017-04-14 |
| Receiver_spartn6_v1\work\rx_sm\verilog.asm | 24283 | 2017-04-14 |
| Receiver_spartn6_v1\work\rx_sm\_primary.dat | 3090 | 2017-04-14 |
| Receiver_spartn6_v1\work\rx_sm\_primary.vhd | 686 | 2017-04-14 |
| Receiver_spartn6_v1\work\tb | 0 | 2017-04-06 |
| Receiver_spartn6_v1\work\tb\verilog.asm | 9368 | 2017-04-14 |
| Receiver_spartn6_v1\work\tb\_primary.dat | 1059 | 2017-04-14 |
| Receiver_spartn6_v1\work\tb\_primary.vhd | 64 | 2017-04-14 |
| Receiver_spartn6_v1\work\top_rx_7seg_design | 0 | 2017-04-06 |
| Receiver_spartn6_v1\work\top_rx_7seg_design\verilog.asm | 3737 | 2017-04-14 |
| Receiver_spartn6_v1\work\top_rx_7seg_design\_primary.dat | 555 | 2017-04-14 |
| Receiver_spartn6_v1\work\top_rx_7seg_design\_primary.vhd | 365 | 2017-04-14 |
| Receiver_spartn6_v1\work\top_uart_rx | 0 | 2017-04-06 |
| Receiver_spartn6_v1\work\top_uart_rx\verilog.asm | 4297 | 2017-04-14 |
| Receiver_spartn6_v1\work\top_uart_rx\_primary.dat | 660 | 2017-04-14 |
| Receiver_spartn6_v1\work\top_uart_rx\_primary.vhd | 332 | 2017-04-14 |
| Receiver_spartn6_v1\work\_info | 1500 | 2017-04-14 |
本网站为编程资源及源代码搜集、介绍的搜索网站，版权归原作者所有！ 粤ICP备11031372号
1999-2046 搜珍网 All Rights Reserved.