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文件名称:mCPU

  • 所属分类：
    其他
  • 标签属性：
    [Windows] [程序]
  • 上传时间：
    2018-03-22
  • 文件大小：
    99kb
  • 已下载：
    0次
  • 提 供 者：
    Eddi****
  • 相关连接：
    无
  • 下载说明：
    别用迅雷下载，失败请重下，重下不扣分！
修正介绍说明

介绍说明－－下载内容来自于网络，使用问题请自行百度

多周期CPU, 可参考程序, 详情请结合网上的实驗报告(Multi cycle CPU, reference program. For details, please combine the experimental report on the Internet)
相关搜索： 多周期CPU cpu vivado

(系统自动生成,下载前可以参看下载内容)

下载文件列表

文件名大小更新时间
mCPU\project_2\project_2.cache\wt\project.wpc 61 2017-12-19
mCPU\project_2\project_2.cache\wt\xsim.wdf 256 2017-12-19
mCPU\project_2\project_2.hw\project_2.lpr 290 2017-12-19
mCPU\project_2\project_2.ip_user_files\README.txt 130 2017-12-19
mCPU\project_2\project_2.sim\sim_1\behav\compile.bat 317 2017-12-19
mCPU\project_2\project_2.sim\sim_1\behav\compile.log 2914 2017-12-19
mCPU\project_2\project_2.sim\sim_1\behav\elaborate.bat 405 2017-12-19
mCPU\project_2\project_2.sim\sim_1\behav\elaborate.log 7600 2017-12-19
mCPU\project_2\project_2.sim\sim_1\behav\glbl.v 1470 2017-01-24
mCPU\project_2\project_2.sim\sim_1\behav\mCPU_sim.tcl 460 2017-12-19
mCPU\project_2\project_2.sim\sim_1\behav\mCPU_sim_behav.wdb 31331 2017-12-19
mCPU\project_2\project_2.sim\sim_1\behav\mCPU_sim_vlog.prj 1195 2017-12-19
mCPU\project_2\project_2.sim\sim_1\behav\simulate.bat 279 2017-12-19
mCPU\project_2\project_2.sim\sim_1\behav\simulate.log 0 2017-12-19
mCPU\project_2\project_2.sim\sim_1\behav\webtalk.jou 781 2017-12-19
mCPU\project_2\project_2.sim\sim_1\behav\webtalk.log 1182 2017-12-19
mCPU\project_2\project_2.sim\sim_1\behav\xelab.pb 12378 2017-12-19
mCPU\project_2\project_2.sim\sim_1\behav\xsim.dir\mCPU_sim_behav\Compile_Options.txt 243 2017-12-19
mCPU\project_2\project_2.sim\sim_1\behav\xsim.dir\mCPU_sim_behav\mCPU_sim_behav_13880_1513618662.btree 0 2017-12-19
mCPU\project_2\project_2.sim\sim_1\behav\xsim.dir\mCPU_sim_behav\TempBreakPointFile.txt 29 2017-12-19
mCPU\project_2\project_2.sim\sim_1\behav\xsim.dir\mCPU_sim_behav\webtalk\.xsim_webtallk.info 55 2017-12-19
mCPU\project_2\project_2.sim\sim_1\behav\xsim.dir\mCPU_sim_behav\webtalk\usage_statistics_ext_xsim.html 3667 2017-12-19
mCPU\project_2\project_2.sim\sim_1\behav\xsim.dir\mCPU_sim_behav\webtalk\usage_statistics_ext_xsim.xml 3572 2017-12-19
mCPU\project_2\project_2.sim\sim_1\behav\xsim.dir\mCPU_sim_behav\xsim.dbg 26740 2017-12-19
mCPU\project_2\project_2.sim\sim_1\behav\xsim.dir\mCPU_sim_behav\xsim.mem 6503 2017-12-19
mCPU\project_2\project_2.sim\sim_1\behav\xsim.dir\mCPU_sim_behav\xsim.reloc 4694 2017-12-19
mCPU\project_2\project_2.sim\sim_1\behav\xsim.dir\mCPU_sim_behav\xsim.rtti 311 2017-12-19
mCPU\project_2\project_2.sim\sim_1\behav\xsim.dir\mCPU_sim_behav\xsim.svtype 89 2017-12-19
mCPU\project_2\project_2.sim\sim_1\behav\xsim.dir\mCPU_sim_behav\xsim.type 24 2017-12-19
mCPU\project_2\project_2.sim\sim_1\behav\xsim.dir\mCPU_sim_behav\xsim.xdbg 22416 2017-12-19
mCPU\project_2\project_2.sim\sim_1\behav\xsim.dir\mCPU_sim_behav\xsimcrash.log 0 2017-12-19
mCPU\project_2\project_2.sim\sim_1\behav\xsim.dir\mCPU_sim_behav\xsimk.exe 168230 2017-12-19
mCPU\project_2\project_2.sim\sim_1\behav\xsim.dir\mCPU_sim_behav\xsimkernel.log 223 2017-12-19
mCPU\project_2\project_2.sim\sim_1\behav\xsim.dir\xil_defaultlib\@a@l@u.sdb 3439 2017-12-19
mCPU\project_2\project_2.sim\sim_1\behav\xsim.dir\xil_defaultlib\@alu@late.sdb 944 2017-12-19
mCPU\project_2\project_2.sim\sim_1\behav\xsim.dir\xil_defaultlib\@contrl@unit.sdb 9631 2017-12-19
mCPU\project_2\project_2.sim\sim_1\behav\xsim.dir\xil_defaultlib\@data@late.sdb 947 2017-12-19
mCPU\project_2\project_2.sim\sim_1\behav\xsim.dir\xil_defaultlib\@data@memory.sdb 2695 2017-12-19
mCPU\project_2\project_2.sim\sim_1\behav\xsim.dir\xil_defaultlib\@data@seltr.sdb 913 2017-12-19
mCPU\project_2\project_2.sim\sim_1\behav\xsim.dir\xil_defaultlib\@extend.sdb 1659 2017-12-19
mCPU\project_2\project_2.sim\sim_1\behav\xsim.dir\xil_defaultlib\@ins@late.sdb 939 2017-12-19
mCPU\project_2\project_2.sim\sim_1\behav\xsim.dir\xil_defaultlib\@ins@memory.sdb 2093 2017-12-19
mCPU\project_2\project_2.sim\sim_1\behav\xsim.dir\xil_defaultlib\@p@c.sdb 1972 2017-12-19
mCPU\project_2\project_2.sim\sim_1\behav\xsim.dir\xil_defaultlib\@p@c@addr.sdb 1270 2017-12-19
mCPU\project_2\project_2.sim\sim_1\behav\xsim.dir\xil_defaultlib\@reg@file.sdb 2738 2017-12-19
mCPU\project_2\project_2.sim\sim_1\behav\xsim.dir\xil_defaultlib\glbl.sdb 3875 2017-12-19
mCPU\project_2\project_2.sim\sim_1\behav\xsim.dir\xil_defaultlib\m@c@p@u.sdb 5045 2017-12-19
mCPU\project_2\project_2.sim\sim_1\behav\xsim.dir\xil_defaultlib\m@c@p@u_sim.sdb 1944 2017-12-19
mCPU\project_2\project_2.sim\sim_1\behav\xsim.dir\xil_defaultlib\xil_defaultlib.rlx 1459 2017-12-19
mCPU\project_2\project_2.sim\sim_1\behav\xsim.dir\xsim.svtype 8 2017-12-19
mCPU\project_2\project_2.sim\sim_1\behav\xsim.ini 40 2017-12-19
mCPU\project_2\project_2.sim\sim_1\behav\xvlog.log 2914 2017-12-19
mCPU\project_2\project_2.sim\sim_1\behav\xvlog.pb 5196 2017-12-19
mCPU\project_2\project_2.srcs\sim_1\new\mCPU_sim.v 955 2017-12-19
mCPU\project_2\project_2.srcs\sources_1\new\ALU.v 1446 2017-12-19
mCPU\project_2\project_2.srcs\sources_1\new\AluLate.v 226 2017-12-19
mCPU\project_2\project_2.srcs\sources_1\new\ContrlUnit.v 6234 2017-12-19
mCPU\project_2\project_2.srcs\sources_1\new\DataLate.v 230 2017-12-19
mCPU\project_2\project_2.srcs\sources_1\new\DataMemory.v 826 2017-12-19
mCPU\project_2\project_2.srcs\sources_1\new\DataSeltr.v 198 2017-12-19
mCPU\project_2\project_2.srcs\sources_1\new\Extend.v 593 2017-12-19
mCPU\project_2\project_2.srcs\sources_1\new\InsLate.v 222 2017-12-19
mCPU\project_2\project_2.srcs\sources_1\new\InsMemory.v 725 2017-12-19
mCPU\project_2\project_2.srcs\sources_1\new\mCPU.v 2097 2017-12-19
mCPU\project_2\project_2.srcs\sources_1\new\OpLate.v 0 2017-12-19
mCPU\project_2\project_2.srcs\sources_1\new\PC.v 796 2017-12-19
mCPU\project_2\project_2.srcs\sources_1\new\PCAddr.v 298 2017-12-19
mCPU\project_2\project_2.srcs\sources_1\new\RegFile.v 1034 2017-12-19
mCPU\project_2\project_2.xpr 9494 2017-12-19
mCPU\project_2\project_2.sim\sim_1\behav\.Xil\Webtalk-32764-For93TMe\webtalk 0 2017-12-19
mCPU\project_2\project_2.sim\sim_1\behav\xsim.dir\mCPU_sim_behav\webtalk 0 2017-12-19
mCPU\project_2\project_2.sim\sim_1\behav\.Xil\Webtalk-32764-For93TMe 0 2017-12-19
mCPU\project_2\project_2.sim\sim_1\behav\xsim.dir\mCPU_sim_behav 0 2017-12-19
mCPU\project_2\project_2.sim\sim_1\behav\xsim.dir\xil_defaultlib 0 2017-12-19
mCPU\project_2\project_2.sim\sim_1\behav\.Xil 0 2017-12-19
mCPU\project_2\project_2.sim\sim_1\behav\xsim.dir 0 2017-12-19
mCPU\project_2\project_2.sim\sim_1\behav 0 2017-12-19
mCPU\project_2\project_2.srcs\sim_1\new 0 2017-12-19
mCPU\project_2\project_2.srcs\sources_1\new 0 2017-12-19
mCPU\project_2\project_2.cache\wt 0 2017-12-19
mCPU\project_2\project_2.sim\sim_1 0 2017-12-19
mCPU\project_2\project_2.srcs\sim_1 0 2017-12-19
mCPU\project_2\project_2.srcs\sources_1 0 2017-12-19
mCPU\project_2\project_2.cache 0 2017-12-19
mCPU\project_2\project_2.hw 0 2017-12-19
mCPU\project_2\project_2.ip_user_files 0 2017-12-19
mCPU\project_2\project_2.sim 0 2017-12-19
mCPU\project_2\project_2.srcs 0 2017-12-19
mCPU\project_2 0 2017-12-19
mCPU 0 2017-12-19

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