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文件名称:BMD_design_gen2_x4_Chipscope

  • 所属分类：
    VHDL/FPGA/Verilog
  • 标签属性：
    [VHDL] [源码]
  • 上传时间：
    2018-03-27
  • 文件大小：
    8.92mb
  • 已下载：
    0次
  • 提 供 者：
    chunji******
  • 相关连接：
    无
  • 下载说明：
    别用迅雷下载，失败请重下，重下不扣分！
修正介绍说明

介绍说明－－下载内容来自于网络，使用问题请自行百度

此文件是Xilinx公司的PCIE演示文档，可验证实现PCIE的基本功能(This file is Xilinx's PCIE demonstration document that validates the basic functions of the implementation of PCIE)
相关搜索： fpga Xilinx pcie

(系统自动生成,下载前可以参看下载内容)

下载文件列表

文件名大小更新时间
BMD_design_gen2_x4_Chipscope\bmd.cdc 30571 2014-08-06
BMD_design_gen2_x4_Chipscope\BMD.v 12337 2014-08-06
BMD_design_gen2_x4_Chipscope\BMD_64_RX_ENGINE.v 17139 2009-10-22
BMD_design_gen2_x4_Chipscope\BMD_64_TX_ENGINE.v 27266 2009-10-22
BMD_design_gen2_x4_Chipscope\BMD_CFG_CTRL.v 5098 2009-10-22
BMD_design_gen2_x4_Chipscope\BMD_design_gen2_x4.gise 15286 2018-01-11
BMD_design_gen2_x4_Chipscope\BMD_design_gen2_x4.xise 42028 2018-01-11
BMD_design_gen2_x4_Chipscope\BMD_EP.v 25469 2014-08-06
BMD_design_gen2_x4_Chipscope\BMD_EP_MEM.v 25212 2014-08-06
BMD_design_gen2_x4_Chipscope\BMD_EP_MEM_ACCESS.v 16932 2014-08-06
BMD_design_gen2_x4_Chipscope\BMD_GEN2.v 9087 2014-08-06
BMD_design_gen2_x4_Chipscope\BMD_INTR_CTRL.v 8647 2009-10-22
BMD_design_gen2_x4_Chipscope\BMD_INTR_CTRL_DELAY.v 3398 2009-10-22
BMD_design_gen2_x4_Chipscope\BMD_PCIE_20.v 1083 2009-10-22
BMD_design_gen2_x4_Chipscope\BMD_RD_THROTTLE.v 7624 2009-10-22
BMD_design_gen2_x4_Chipscope\BMD_TO_CTRL.v 2379 2009-10-22
BMD_design_gen2_x4_Chipscope\BMD_TX_ENGINE_summary.html 4105 2014-08-06
BMD_design_gen2_x4_Chipscope\gtx_drp_chanalign_fix_3752_v6.v 6942 2014-08-05
BMD_design_gen2_x4_Chipscope\gtx_rx_valid_filter_v6.v 12103 2014-08-05
BMD_design_gen2_x4_Chipscope\gtx_tx_sync_rate_v6.v 14596 2014-08-05
BMD_design_gen2_x4_Chipscope\gtx_wrapper_v6.v 26511 2014-08-05
BMD_design_gen2_x4_Chipscope\iseconfig\BMD_design_gen2_x4.projectmgr 8104 2018-01-11
BMD_design_gen2_x4_Chipscope\iseconfig\BMD_TX_ENGINE.xreport 21166 2014-08-06
BMD_design_gen2_x4_Chipscope\iseconfig\filter.filter 650 2014-08-06
BMD_design_gen2_x4_Chipscope\iseconfig\xilinx_pcie_2_0_ep_v6.xreport 21219 2018-01-11
BMD_design_gen2_x4_Chipscope\pcie_2_0_v6.v 82207 2014-08-05
BMD_design_gen2_x4_Chipscope\pcie_app_v6.cmd_log 193 2014-08-06
BMD_design_gen2_x4_Chipscope\pcie_app_v6.lso 6 2014-08-06
BMD_design_gen2_x4_Chipscope\pcie_app_v6.ngc 944004 2014-08-06
BMD_design_gen2_x4_Chipscope\pcie_app_v6.ngr 1239650 2014-08-06
BMD_design_gen2_x4_Chipscope\pcie_app_v6.prj 373 2014-08-06
BMD_design_gen2_x4_Chipscope\pcie_app_v6.stx 0 2014-08-06
BMD_design_gen2_x4_Chipscope\pcie_app_v6.syr 82960 2014-08-06
BMD_design_gen2_x4_Chipscope\pcie_app_v6.xst 1085 2014-08-06
BMD_design_gen2_x4_Chipscope\pcie_app_v6_envsettings.html 9075 2014-08-06
BMD_design_gen2_x4_Chipscope\pcie_app_v6_summary.html 5711 2014-08-06
BMD_design_gen2_x4_Chipscope\pcie_app_v6_xst.xrpt 16513 2014-08-06
BMD_design_gen2_x4_Chipscope\pcie_brams_v6.v 8684 2014-08-05
BMD_design_gen2_x4_Chipscope\pcie_bram_top_v6.v 6038 2014-08-05
BMD_design_gen2_x4_Chipscope\pcie_bram_v6.v 11739 2014-08-05
BMD_design_gen2_x4_Chipscope\pcie_clocking_v6.v 11538 2014-08-05
BMD_design_gen2_x4_Chipscope\pcie_gtx_v6.v 24312 2014-08-05
BMD_design_gen2_x4_Chipscope\pcie_pipe_lane_v6.v 12792 2014-08-05
BMD_design_gen2_x4_Chipscope\pcie_pipe_misc_v6.v 7726 2014-08-05
BMD_design_gen2_x4_Chipscope\pcie_pipe_v6.v 36367 2014-08-05
BMD_design_gen2_x4_Chipscope\pcie_reset_delay_v6.v 4060 2014-08-05
BMD_design_gen2_x4_Chipscope\pcie_upconfig_fix_3451_v6.v 7377 2014-08-05
BMD_design_gen2_x4_Chipscope\usage_statistics_webtalk.html 334760 2014-08-06
BMD_design_gen2_x4_Chipscope\v6_pcie_v1_7.v 53245 2014-08-05
BMD_design_gen2_x4_Chipscope\v6_pci_exp_64b_app.v 13597 2014-08-06
BMD_design_gen2_x4_Chipscope\webtalk.log 703 2014-08-06
BMD_design_gen2_x4_Chipscope\webtalk_pn.xml 3037 2014-08-06
BMD_design_gen2_x4_Chipscope\xilinx_pcie_2_0_ep_v6.bgn 8450 2014-08-06
BMD_design_gen2_x4_Chipscope\xilinx_pcie_2_0_ep_v6.bit 9232570 2014-08-06
BMD_design_gen2_x4_Chipscope\xilinx_pcie_2_0_ep_v6.bld 1701 2014-08-06
BMD_design_gen2_x4_Chipscope\xilinx_pcie_2_0_ep_v6.cmd_log 6035 2014-08-06
BMD_design_gen2_x4_Chipscope\xilinx_pcie_2_0_ep_v6.drc 521 2014-08-06
BMD_design_gen2_x4_Chipscope\xilinx_pcie_2_0_ep_v6.lso 6 2014-08-06
BMD_design_gen2_x4_Chipscope\xilinx_pcie_2_0_ep_v6.ncd 2682503 2014-08-06
BMD_design_gen2_x4_Chipscope\xilinx_pcie_2_0_ep_v6.ngc 1529476 2014-08-06
BMD_design_gen2_x4_Chipscope\xilinx_pcie_2_0_ep_v6.ngd 6862893 2014-08-06
BMD_design_gen2_x4_Chipscope\xilinx_pcie_2_0_ep_v6.ngr 2562151 2014-08-06
BMD_design_gen2_x4_Chipscope\xilinx_pcie_2_0_ep_v6.pad 43144 2014-08-06
BMD_design_gen2_x4_Chipscope\xilinx_pcie_2_0_ep_v6.par 18028 2014-08-06
BMD_design_gen2_x4_Chipscope\xilinx_pcie_2_0_ep_v6.pcf 1026822 2014-08-06
BMD_design_gen2_x4_Chipscope\xilinx_pcie_2_0_ep_v6.prj 982 2014-08-06
BMD_design_gen2_x4_Chipscope\xilinx_pcie_2_0_ep_v6.ptwx 21483 2014-08-06
BMD_design_gen2_x4_Chipscope\xilinx_pcie_2_0_ep_v6.stx 0 2014-08-06
BMD_design_gen2_x4_Chipscope\xilinx_pcie_2_0_ep_v6.syr 219392 2014-08-06
BMD_design_gen2_x4_Chipscope\xilinx_pcie_2_0_ep_v6.twr 205993 2014-08-06
BMD_design_gen2_x4_Chipscope\xilinx_pcie_2_0_ep_v6.twx 231173 2014-08-06
BMD_design_gen2_x4_Chipscope\xilinx_pcie_2_0_ep_v6.unroutes 155 2014-08-06
BMD_design_gen2_x4_Chipscope\xilinx_pcie_2_0_ep_v6.ut 743 2014-08-06
BMD_design_gen2_x4_Chipscope\xilinx_pcie_2_0_ep_v6.v 19203 2014-08-05
BMD_design_gen2_x4_Chipscope\xilinx_pcie_2_0_ep_v6.xpi 45 2014-08-06
BMD_design_gen2_x4_Chipscope\xilinx_pcie_2_0_ep_v6.xst 1115 2014-08-06
BMD_design_gen2_x4_Chipscope\xilinx_pcie_2_0_ep_v6_04_lane_gen2_xc6vlx240t-ff1156-1_ML605.ucf 7057 2014-08-05
BMD_design_gen2_x4_Chipscope\xilinx_pcie_2_0_ep_v6_bitgen.xwbt 313 2014-08-06
BMD_design_gen2_x4_Chipscope\xilinx_pcie_2_0_ep_v6_cs.blc 989 2014-08-06
BMD_design_gen2_x4_Chipscope\xilinx_pcie_2_0_ep_v6_cs.ngc 3531609 2014-08-06
BMD_design_gen2_x4_Chipscope\xilinx_pcie_2_0_ep_v6_envsettings.html 12848 2018-01-11
BMD_design_gen2_x4_Chipscope\xilinx_pcie_2_0_ep_v6_guide.ncd 2682503 2014-08-06
BMD_design_gen2_x4_Chipscope\xilinx_pcie_2_0_ep_v6_map.map 16390 2014-08-06
BMD_design_gen2_x4_Chipscope\xilinx_pcie_2_0_ep_v6_map.mrp 41955 2014-08-06
BMD_design_gen2_x4_Chipscope\xilinx_pcie_2_0_ep_v6_map.ncd 1146042 2014-08-06
BMD_design_gen2_x4_Chipscope\xilinx_pcie_2_0_ep_v6_map.ngm 13185693 2014-08-06
BMD_design_gen2_x4_Chipscope\xilinx_pcie_2_0_ep_v6_map.xrpt 38957 2014-08-06
BMD_design_gen2_x4_Chipscope\xilinx_pcie_2_0_ep_v6_ngdbuild.xrpt 18069 2014-08-06
BMD_design_gen2_x4_Chipscope\xilinx_pcie_2_0_ep_v6_pad.csv 43177 2014-08-06
BMD_design_gen2_x4_Chipscope\xilinx_pcie_2_0_ep_v6_pad.txt 227344 2014-08-06
BMD_design_gen2_x4_Chipscope\xilinx_pcie_2_0_ep_v6_par.xrpt 464642 2014-08-06
BMD_design_gen2_x4_Chipscope\xilinx_pcie_2_0_ep_v6_summary.html 21320 2018-01-11
BMD_design_gen2_x4_Chipscope\xilinx_pcie_2_0_ep_v6_summary.xml 409 2014-08-06
BMD_design_gen2_x4_Chipscope\xilinx_pcie_2_0_ep_v6_usage.xml 383328 2014-08-06
BMD_design_gen2_x4_Chipscope\xilinx_pcie_2_0_ep_v6_xst.xrpt 18487 2014-08-06
BMD_design_gen2_x4_Chipscope\xlnx_auto_0_xdb\cst.xbcd 341231 2014-08-06
BMD_design_gen2_x4_Chipscope\xst\work\work.sdbl 766728 2014-08-06
BMD_design_gen2_x4_Chipscope\xst\work\work.sdbx 704 2014-08-06
BMD_design_gen2_x4_Chipscope\_ngo\cs_icon_pro\coregen.cgc 16248 2014-08-06
BMD_design_gen2_x4_Chipscope\_ngo\cs_icon_pro\coregen.cgp 520 2014-08-06

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