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文件名称:Verilog

  • 所属分类：
    VHDL/FPGA/Verilog
  • 标签属性：
    [VHDL] [源码]
  • 上传时间：
    2018-04-19
  • 文件大小：
    19.56mb
  • 已下载：
    0次
  • 提 供 者：
    高*****
  • 相关连接：
    无
  • 下载说明：
    别用迅雷下载，失败请重下，重下不扣分！
修正介绍说明

介绍说明－－下载内容来自于网络，使用问题请自行百度

01-08例程为数电基础部分：比较简单，代码中可明显看出或是有中文注释，或是在工程代码主文件最前面有文字注释说明。(The 01-08 routine is the basic part of the digital power: it is relatively simple. It can be clearly seen in the code or have Chinese annotations, or in the front of the master code of the engineering code.)
相关搜索： Project_Verilog

(系统自动生成,下载前可以参看下载内容)

下载文件列表

文件名大小更新时间
08_Project_Verilog\01_gate\auto_project.ipf 21182 2017-02-28
08_Project_Verilog\01_gate\auto_project_1.ipf 21260 2017-02-24
08_Project_Verilog\01_gate\gate.cfi 410 2015-08-31
08_Project_Verilog\01_gate\gate.gise 12657 2016-10-05
08_Project_Verilog\01_gate\gate.mcs 936773 2015-08-31
08_Project_Verilog\01_gate\gate.prm 589 2015-08-31
08_Project_Verilog\01_gate\gate.ucf 52 2015-08-31
08_Project_Verilog\01_gate\gate.xise 36182 2016-09-02
08_Project_Verilog\01_gate\impact.xsl 1477 2017-03-06
08_Project_Verilog\01_gate\impact_impact.xwbt 220 2017-03-06
08_Project_Verilog\01_gate\iseconfig\gate.projectmgr 5663 2016-10-05
08_Project_Verilog\01_gate\iseconfig\my_and.xreport 20817 2017-03-09
08_Project_Verilog\01_gate\my_and.bgn 6712 2016-09-02
08_Project_Verilog\01_gate\my_and.bit 340695 2016-09-02
08_Project_Verilog\01_gate\my_and.bld 1010 2016-09-02
08_Project_Verilog\01_gate\my_and.cmd_log 1308 2016-09-02
08_Project_Verilog\01_gate\my_and.drc 190 2016-09-02
08_Project_Verilog\01_gate\my_and.lso 6 2016-09-02
08_Project_Verilog\01_gate\my_and.ncd 3010 2016-09-02
08_Project_Verilog\01_gate\my_and.ngc 1204 2016-09-02
08_Project_Verilog\01_gate\my_and.ngd 2071 2016-09-02
08_Project_Verilog\01_gate\my_and.ngr 779 2016-09-02
08_Project_Verilog\01_gate\my_and.pad 6776 2016-09-02
08_Project_Verilog\01_gate\my_and.par 6182 2016-09-02
08_Project_Verilog\01_gate\my_and.pcf 374 2016-09-02
08_Project_Verilog\01_gate\my_and.prj 25 2016-09-02
08_Project_Verilog\01_gate\my_and.ptwx 16463 2016-09-02
08_Project_Verilog\01_gate\my_and.stx 0 2016-09-02
08_Project_Verilog\01_gate\my_and.syr 9664 2016-09-02
08_Project_Verilog\01_gate\my_and.twr 1978 2016-09-02
08_Project_Verilog\01_gate\my_and.twx 18672 2016-09-02
08_Project_Verilog\01_gate\my_and.unroutes 161 2016-09-02
08_Project_Verilog\01_gate\my_and.ut 553 2016-09-02
08_Project_Verilog\01_gate\my_and.v 695 2011-06-25
08_Project_Verilog\01_gate\my_and.xpi 46 2016-09-02
08_Project_Verilog\01_gate\my_and.xst 1067 2016-09-02
08_Project_Verilog\01_gate\my_and_bitgen.xwbt 230 2016-09-02
08_Project_Verilog\01_gate\my_and_envsettings.html 13648 2017-03-09
08_Project_Verilog\01_gate\my_and_guide.ncd 3010 2016-09-02
08_Project_Verilog\01_gate\my_and_map.map 6041 2016-09-02
08_Project_Verilog\01_gate\my_and_map.mrp 8041 2016-09-02
08_Project_Verilog\01_gate\my_and_map.ncd 2238 2016-09-02
08_Project_Verilog\01_gate\my_and_map.ngm 3500 2016-09-02
08_Project_Verilog\01_gate\my_and_map.xrpt 19657 2016-09-02
08_Project_Verilog\01_gate\my_and_ngdbuild.xrpt 5054 2016-09-02
08_Project_Verilog\01_gate\my_and_pad.csv 6808 2016-09-02
08_Project_Verilog\01_gate\my_and_pad.txt 29493 2016-09-02
08_Project_Verilog\01_gate\my_and_par.xrpt 75720 2016-09-02
08_Project_Verilog\01_gate\my_and_summary.html 13558 2017-03-09
08_Project_Verilog\01_gate\my_and_summary.xml 408 2016-09-02
08_Project_Verilog\01_gate\my_and_usage.xml 5420 2016-09-02
08_Project_Verilog\01_gate\my_and_xst.xrpt 10570 2016-09-02
08_Project_Verilog\01_gate\output.txt 128 2017-02-28
08_Project_Verilog\01_gate\par_usage_statistics.html 4130 2016-09-02
08_Project_Verilog\01_gate\usage_statistics_webtalk.html 5306 2017-03-06
08_Project_Verilog\01_gate\webtalk.log 696 2017-03-06
08_Project_Verilog\01_gate\webtalk_impact.xml 2022 2017-03-06
08_Project_Verilog\01_gate\webtalk_pn.xml 3157 2016-09-02
08_Project_Verilog\01_gate\xlnx_auto_0_xdb\cst.xbcd 461 2016-09-02
08_Project_Verilog\01_gate\xst\work\work.sdbl 608 2016-09-02
08_Project_Verilog\01_gate\xst\work\work.sdbx 68 2016-09-02
08_Project_Verilog\01_gate\_ngo\netlist.lst 57 2016-09-02
08_Project_Verilog\01_gate\_xmsgs\bitgen.xmsgs 367 2016-09-02
08_Project_Verilog\01_gate\_xmsgs\map.xmsgs 1454 2016-09-02
08_Project_Verilog\01_gate\_xmsgs\ngdbuild.xmsgs 367 2016-09-02
08_Project_Verilog\01_gate\_xmsgs\par.xmsgs 1151 2016-09-02
08_Project_Verilog\01_gate\_xmsgs\pn_parser.xmsgs 754 2017-03-09
08_Project_Verilog\01_gate\_xmsgs\trce.xmsgs 1149 2016-09-02
08_Project_Verilog\01_gate\_xmsgs\xst.xmsgs 367 2016-09-02
08_Project_Verilog\02_gate\my_nand\iseconfig\my_nand.projectmgr 5931 2017-03-09
08_Project_Verilog\02_gate\my_nand\iseconfig\my_nand.xreport 20913 2017-03-09
08_Project_Verilog\02_gate\my_nand\my_nand.bgn 6717 2017-03-09
08_Project_Verilog\02_gate\my_nand\my_nand.bit 340696 2017-03-09
08_Project_Verilog\02_gate\my_nand\my_nand.bld 1047 2017-03-09
08_Project_Verilog\02_gate\my_nand\my_nand.cfi 430 2015-08-31
08_Project_Verilog\02_gate\my_nand\my_nand.cmd_log 1418 2017-03-09
08_Project_Verilog\02_gate\my_nand\my_nand.drc 192 2017-03-09
08_Project_Verilog\02_gate\my_nand\my_nand.gise 12665 2017-03-09
08_Project_Verilog\02_gate\my_nand\my_nand.lso 6 2017-03-09
08_Project_Verilog\02_gate\my_nand\my_nand.mcs 936773 2015-08-31
08_Project_Verilog\02_gate\my_nand\my_nand.ncd 2894 2017-03-09
08_Project_Verilog\02_gate\my_nand\my_nand.ngc 1203 2017-03-09
08_Project_Verilog\02_gate\my_nand\my_nand.ngd 2066 2017-03-09
08_Project_Verilog\02_gate\my_nand\my_nand.ngr 896 2017-03-09
08_Project_Verilog\02_gate\my_nand\my_nand.pad 6778 2017-03-09
08_Project_Verilog\02_gate\my_nand\my_nand.par 6189 2017-03-09
08_Project_Verilog\02_gate\my_nand\my_nand.pcf 374 2017-03-09
08_Project_Verilog\02_gate\my_nand\my_nand.prj 26 2017-03-09
08_Project_Verilog\02_gate\my_nand\my_nand.prm 629 2015-08-31
08_Project_Verilog\02_gate\my_nand\my_nand.ptwx 16463 2017-03-09
08_Project_Verilog\02_gate\my_nand\my_nand.stx 0 2017-03-09
08_Project_Verilog\02_gate\my_nand\my_nand.syr 9727 2017-03-09
08_Project_Verilog\02_gate\my_nand\my_nand.twr 1987 2017-03-09
08_Project_Verilog\02_gate\my_nand\my_nand.twx 18681 2017-03-09
08_Project_Verilog\02_gate\my_nand\my_nand.ucf 51 2017-03-09
08_Project_Verilog\02_gate\my_nand\my_nand.unroutes 161 2017-03-09
08_Project_Verilog\02_gate\my_nand\my_nand.ut 553 2017-03-09
08_Project_Verilog\02_gate\my_nand\my_nand.v 860 2017-03-09
08_Project_Verilog\02_gate\my_nand\my_nand.xise 36200 2017-03-09
08_Project_Verilog\02_gate\my_nand\my_nand.xpi 46 2017-03-09

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