文件名称:PLL
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- 上传时间：2018-04-28
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文件大小：213kb
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已下载：0次
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介绍说明－－下载内容来自于网络，使用问题请自行百度
本次的设计主要任务是学会调用锁相环 IP 核，并对其进行仿真，
具体要求如下：（1）熟练掌握调用锁相环 IP 核的详细步骤。将 50M
的时钟分成 20MHz 和 100MHz 两个时钟（2）对锁相环进行仿真，验证
调用的锁相环的正确性。(The main task of this design is to learn to call the phase-locked loop IP core.)
具体要求如下：（1）熟练掌握调用锁相环 IP 核的详细步骤。将 50M
的时钟分成 20MHz 和 100MHz 两个时钟（2）对锁相环进行仿真，验证
调用的锁相环的正确性。(The main task of this design is to learn to call the phase-locked loop IP core.)
相关搜索： quartus II
verilog hdl
(系统自动生成,下载前可以参看下载内容)
下载文件列表
| 文件名 | 大小 | 更新时间 |
|---|---|---|
| PLL | 0 | 2018-04-27 |
| PLL\db | 0 | 2018-04-27 |
| PLL\db\logic_util_heursitic.dat | 0 | 2018-04-01 |
| PLL\db\mypll_altpll.v | 4720 | 2018-04-01 |
| PLL\db\pll.(0).cnf.cdb | 993 | 2018-04-01 |
| PLL\db\pll.(0).cnf.hdb | 699 | 2018-04-01 |
| PLL\db\pll.(1).cnf.cdb | 1963 | 2018-04-01 |
| PLL\db\pll.(1).cnf.hdb | 1224 | 2018-04-01 |
| PLL\db\pll.(2).cnf.cdb | 1739 | 2018-04-01 |
| PLL\db\pll.(2).cnf.hdb | 1026 | 2018-04-01 |
| PLL\db\pll.(3).cnf.cdb | 1617 | 2018-04-01 |
| PLL\db\pll.(3).cnf.hdb | 982 | 2018-04-01 |
| PLL\db\pll.cbx.xml | 199 | 2018-04-01 |
| PLL\db\pll.cmp.rdb | 9299 | 2018-04-01 |
| PLL\db\pll.cmp_merge.kpt | 208 | 2018-04-01 |
| PLL\db\pll.db_info | 139 | 2018-04-27 |
| PLL\db\pll.hier_info | 2279 | 2018-04-01 |
| PLL\db\pll.hif | 2801 | 2018-04-01 |
| PLL\db\pll.ipinfo | 288 | 2018-04-27 |
| PLL\db\pll.lpc.html | 814 | 2018-04-01 |
| PLL\db\pll.lpc.rdb | 486 | 2018-04-01 |
| PLL\db\pll.lpc.txt | 1960 | 2018-04-01 |
| PLL\db\pll.map.ammdb | 122 | 2018-04-01 |
| PLL\db\pll.map.bpm | 709 | 2018-04-01 |
| PLL\db\pll.map.cdb | 2914 | 2018-04-01 |
| PLL\db\pll.map.hdb | 11472 | 2018-04-01 |
| PLL\db\pll.map.kpt | 348 | 2018-04-01 |
| PLL\db\pll.map.logdb | 4 | 2018-04-01 |
| PLL\db\pll.map.qmsg | 20015 | 2018-04-01 |
| PLL\db\pll.map.rdb | 1304 | 2018-04-01 |
| PLL\db\pll.map_bb.cdb | 1749 | 2018-04-01 |
| PLL\db\pll.map_bb.hdb | 9850 | 2018-04-01 |
| PLL\db\pll.map_bb.logdb | 4 | 2018-04-01 |
| PLL\db\pll.pre_map.hdb | 18964 | 2018-04-01 |
| PLL\db\pll.pti_db_list.ddb | 176 | 2018-04-01 |
| PLL\db\pll.root_partition.map.reg_db.cdb | 193 | 2018-04-01 |
| PLL\db\pll.rtlv.hdb | 16891 | 2018-04-01 |
| PLL\db\pll.rtlv_sg.cdb | 4601 | 2018-04-01 |
| PLL\db\pll.rtlv_sg_swap.cdb | 3510 | 2018-04-01 |
| PLL\db\pll.sgdiff.cdb | 2639 | 2018-04-01 |
| PLL\db\pll.sgdiff.hdb | 15858 | 2018-04-01 |
| PLL\db\pll.sld_design_entry.sci | 201 | 2018-04-27 |
| PLL\db\pll.sld_design_entry_dsc.sci | 201 | 2018-04-01 |
| PLL\db\pll.smart_action.txt | 5 | 2018-04-01 |
| PLL\db\pll.syn_hier_info | 0 | 2018-04-01 |
| PLL\db\pll.tis_db_list.ddb | 176 | 2018-04-01 |
| PLL\db\pll.tmw_info | 58 | 2018-04-27 |
| PLL\incremental_db | 0 | 2018-04-01 |
| PLL\incremental_db\compiled_partitions | 0 | 2018-04-01 |
| PLL\incremental_db\compiled_partitions\pll.db_info | 139 | 2018-04-01 |
| PLL\incremental_db\compiled_partitions\pll.root_partition.map.cdb | 2658 | 2018-04-01 |
| PLL\incremental_db\compiled_partitions\pll.root_partition.map.dpi | 3605 | 2018-04-01 |
| PLL\incremental_db\compiled_partitions\pll.root_partition.map.hbdb.cdb | 2354 | 2018-04-01 |
| PLL\incremental_db\compiled_partitions\pll.root_partition.map.hbdb.hb_info | 48 | 2018-04-01 |
| PLL\incremental_db\compiled_partitions\pll.root_partition.map.hbdb.hdb | 11154 | 2018-04-01 |
| PLL\incremental_db\compiled_partitions\pll.root_partition.map.hbdb.sig | 32 | 2018-04-01 |
| PLL\incremental_db\compiled_partitions\pll.root_partition.map.hdb | 11361 | 2018-04-01 |
| PLL\incremental_db\compiled_partitions\pll.root_partition.map.kpt | 351 | 2018-04-01 |
| PLL\incremental_db\README | 653 | 2018-04-01 |
| PLL\mypll.ppf | 545 | 2018-04-01 |
| PLL\mypll.qip | 444 | 2018-04-01 |
| PLL\mypll.v | 16638 | 2018-04-01 |
| PLL\mypll_bb.v | 12514 | 2018-04-01 |
| PLL\mypll_inst.v | 138 | 2018-04-01 |
| PLL\node | 0 | 2018-04-01 |
| PLL\node\greybox_tmp | 0 | 2018-04-01 |
| PLL\node\greybox_tmp\cbx_args.txt | 1533 | 2018-04-01 |
| PLL\node\mypll.qip | 0 | 2018-04-01 |
| PLL\node\pll.v | 230 | 2018-04-01 |
| PLL\node\pll_tb.v | 336 | 2018-04-01 |
| PLL\output_files | 0 | 2018-04-01 |
| PLL\output_files\pll.done | 26 | 2018-04-01 |
| PLL\output_files\pll.flow.rpt | 8392 | 2018-04-01 |
| PLL\output_files\pll.map.rpt | 66390 | 2018-04-01 |
| PLL\output_files\pll.map.summary | 454 | 2018-04-01 |
| PLL\pll.qpf | 1269 | 2018-04-01 |
| PLL\pll.qsf | 3442 | 2018-04-01 |
| PLL\pll.qws | 674 | 2018-04-27 |
| PLL\pll_nativelink_simulation.rpt | 957 | 2018-04-26 |
| PLL\simulation | 0 | 2018-04-01 |
| PLL\simulation\modelsim | 0 | 2018-04-26 |
| PLL\simulation\modelsim\modelsim.ini | 11131 | 2018-04-26 |
| PLL\simulation\modelsim\msim_transcript | 2400 | 2018-04-26 |
| PLL\simulation\modelsim\pll_run_msim_rtl_verilog.do | 645 | 2018-04-26 |
| PLL\simulation\modelsim\pll_run_msim_rtl_verilog.do.bak | 645 | 2018-04-01 |
| PLL\simulation\modelsim\pll_run_msim_rtl_verilog.do.bak1 | 645 | 2018-04-01 |
| PLL\simulation\modelsim\pll_run_msim_rtl_verilog.do.bak2 | 645 | 2018-04-18 |
| PLL\simulation\modelsim\pll_run_msim_rtl_verilog.do.bak3 | 645 | 2018-04-18 |
| PLL\simulation\modelsim\rtl_work | 0 | 2018-04-26 |
| PLL\simulation\modelsim\rtl_work\mypll | 0 | 2018-04-26 |
| PLL\simulation\modelsim\rtl_work\mypll\verilog.prw | 2172 | 2018-04-26 |
| PLL\simulation\modelsim\rtl_work\mypll\verilog.psm | 32424 | 2018-04-26 |
| PLL\simulation\modelsim\rtl_work\mypll\_primary.dat | 3745 | 2018-04-26 |
| PLL\simulation\modelsim\rtl_work\mypll\_primary.dbs | 2358 | 2018-04-26 |
| PLL\simulation\modelsim\rtl_work\mypll\_primary.vhd | 301 | 2018-04-26 |
| PLL\simulation\modelsim\rtl_work\mypll_altpll | 0 | 2018-04-26 |
| PLL\simulation\modelsim\rtl_work\mypll_altpll\verilog.prw | 1285 | 2018-04-26 |
| PLL\simulation\modelsim\rtl_work\mypll_altpll\verilog.psm | 15936 | 2018-04-26 |
| PLL\simulation\modelsim\rtl_work\mypll_altpll\_primary.dat | 2051 | 2018-04-26 |
| PLL\simulation\modelsim\rtl_work\mypll_altpll\_primary.dbs | 1720 | 2018-04-26 |
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