本设计实现了一种基于FPGA的数字时钟设计，应用Verilog硬件描述语言进行数字电路设计，采用自顶向下的方法将电路系统逐层分解细化，设计数字时钟总体结构、各模块及相应具体电路。在Quartus II 9.0工具软件环境下编译、仿真。最后下载到FPGA实验平台进行测试。本数字时钟具有显示时间、通过按键校准时间、整点报时等功能。(This design realizes a digital clock design based on FPGA, uses the Verilog hardware descr iption language to design the digital circuit, uses the top down method to decompose the circuit system layer by layer, and designs the overall structure of the digital clock, each module and the corresponding specific circuit. Compile and simulate in Quartus II 9 tool software environment. Finally downloaded to the FPGA experimental platform for testing. This digital clock has the functions of display time, calibration time through keys, timing of whole points and so on.)