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文件名称:DBSTAR_RGMII

  • 所属分类：
    VHDL/FPGA/Verilog
  • 标签属性：
    [HTML]
  • 上传时间：
    2018-07-18
  • 文件大小：
    4.9mb
  • 已下载：
    3次
  • 提 供 者：
    z*****
  • 相关连接：
    无
  • 下载说明：
    别用迅雷下载，失败请重下，重下不扣分！
修正介绍说明

介绍说明－－下载内容来自于网络，使用问题请自行百度

Verilog实现的RGMII和GMII接口转接，适合适配不同PHY芯片接口使用(Verilog implementation of RGMII and GMII interface transfer)
相关搜索： fpga rgmii GMII

(系统自动生成,下载前可以参看下载内容)

下载文件列表

文件名大小更新时间
DBSTAR_RGMII\par\fpga_project_1\fpga_project_1.gprj 644 2018-07-04
DBSTAR_RGMII\par\fpga_project_1\fpga_project_1.gprj.user 2400 2018-07-04
DBSTAR_RGMII\par\fpga_project_1\impl\dualpin_config.ini 219 2018-03-19
DBSTAR_RGMII\par\fpga_project_1\impl\pnr\ao_0.fs 7263452 2018-07-02
DBSTAR_RGMII\par\fpga_project_1\impl\pnr\cmd.do 353 2018-07-02
DBSTAR_RGMII\par\fpga_project_1\impl\pnr\cst.cfg 205 2018-03-26
DBSTAR_RGMII\par\fpga_project_1\impl\pnr\device.cfg 488 2018-07-02
DBSTAR_RGMII\par\fpga_project_1\impl\pnr\fpga_project_1.fs 4619996 2018-03-19
DBSTAR_RGMII\par\fpga_project_1\impl\pnr\fpga_project_1.log 2442 2018-07-02
DBSTAR_RGMII\par\fpga_project_1\impl\pnr\fpga_project_1.pin.html 25055 2018-07-02
DBSTAR_RGMII\par\fpga_project_1\impl\pnr\fpga_project_1.power.html 7866 2018-07-02
DBSTAR_RGMII\par\fpga_project_1\impl\pnr\fpga_project_1.rpt.html 31834 2018-07-02
DBSTAR_RGMII\par\fpga_project_1\impl\pnr\fpga_project_1.rpt.txt 21499 2018-07-02
DBSTAR_RGMII\par\fpga_project_1\impl\pnr\fpga_project_1.timing_paths 7547 2018-07-02
DBSTAR_RGMII\par\fpga_project_1\impl\pnr\fpga_project_1.tr.html 363 2018-07-02
DBSTAR_RGMII\par\fpga_project_1\impl\pnr\fpga_project_1_tr_cata.html 7940 2018-07-02
DBSTAR_RGMII\par\fpga_project_1\impl\pnr\fpga_project_1_tr_content.html 255432 2018-07-02
DBSTAR_RGMII\par\fpga_project_1\impl\synthesize\fpga_project_1.prj 1153 2018-07-02
DBSTAR_RGMII\par\fpga_project_1\impl\synthesize\rev_1\AutoConstraint_top.sdc 582 2018-07-02
DBSTAR_RGMII\par\fpga_project_1\impl\synthesize\rev_1\AutoConstraint_tx_pll.sdc 0 2018-03-19
DBSTAR_RGMII\par\fpga_project_1\impl\synthesize\rev_1\backup\fpga_project_1.srr 3847 2018-03-19
DBSTAR_RGMII\par\fpga_project_1\impl\synthesize\rev_1\dm\layer0.xdm 11255 2018-07-02
DBSTAR_RGMII\par\fpga_project_1\impl\synthesize\rev_1\dump_clock_tree.srs 5534 2018-07-02
DBSTAR_RGMII\par\fpga_project_1\impl\synthesize\rev_1\fpga_project_1.fse 0 2018-07-02
DBSTAR_RGMII\par\fpga_project_1\impl\synthesize\rev_1\fpga_project_1.htm 267 2018-07-02
DBSTAR_RGMII\par\fpga_project_1\impl\synthesize\rev_1\fpga_project_1.map 28 2018-07-02
DBSTAR_RGMII\par\fpga_project_1\impl\synthesize\rev_1\fpga_project_1.sap 1612 2018-07-02
DBSTAR_RGMII\par\fpga_project_1\impl\synthesize\rev_1\fpga_project_1.scf 1390 2018-07-02
DBSTAR_RGMII\par\fpga_project_1\impl\synthesize\rev_1\fpga_project_1.srd 29350 2018-07-02
DBSTAR_RGMII\par\fpga_project_1\impl\synthesize\rev_1\fpga_project_1.srm 27796 2018-07-02
DBSTAR_RGMII\par\fpga_project_1\impl\synthesize\rev_1\fpga_project_1.srr 7988 2018-07-02
DBSTAR_RGMII\par\fpga_project_1\impl\synthesize\rev_1\fpga_project_1.srr.db 8192 2018-07-02
DBSTAR_RGMII\par\fpga_project_1\impl\synthesize\rev_1\fpga_project_1.srs 4389 2018-07-02
DBSTAR_RGMII\par\fpga_project_1\impl\synthesize\rev_1\fpga_project_1.vm 53312 2018-07-02
DBSTAR_RGMII\par\fpga_project_1\impl\synthesize\rev_1\fpga_project_1_cck.rpt 3134 2018-07-02
DBSTAR_RGMII\par\fpga_project_1\impl\synthesize\rev_1\fpga_project_1_cck.rpt.db 8192 2018-07-02
DBSTAR_RGMII\par\fpga_project_1\impl\synthesize\rev_1\fpga_project_1_fpga_mapper.htm 303 2018-07-02
DBSTAR_RGMII\par\fpga_project_1\impl\synthesize\rev_1\fpga_project_1_multi_srs_gen.htm 309 2018-07-02
DBSTAR_RGMII\par\fpga_project_1\impl\synthesize\rev_1\fpga_project_1_premap.htm 288 2018-07-02
DBSTAR_RGMII\par\fpga_project_1\impl\synthesize\rev_1\fpga_project_1_scck.rpt 3571 2018-07-02
DBSTAR_RGMII\par\fpga_project_1\impl\synthesize\rev_1\fpga_project_1_scck.rpt.db 8192 2018-07-02
DBSTAR_RGMII\par\fpga_project_1\impl\synthesize\rev_1\rpt_top.areasrr 3053 2018-07-02
DBSTAR_RGMII\par\fpga_project_1\impl\synthesize\rev_1\rpt_top_areasrr.htm 3266 2018-07-02
DBSTAR_RGMII\par\fpga_project_1\impl\synthesize\rev_1\rpt_tx_pll.areasrr 877 2018-03-19
DBSTAR_RGMII\par\fpga_project_1\impl\synthesize\rev_1\rpt_tx_pll_areasrr.htm 547 2018-03-19
DBSTAR_RGMII\par\fpga_project_1\impl\synthesize\rev_1\run_options.txt 1862 2018-07-02
DBSTAR_RGMII\par\fpga_project_1\impl\synthesize\rev_1\scratchproject.prs 1945 2018-07-02
DBSTAR_RGMII\par\fpga_project_1\impl\synthesize\rev_1\synlog\fpga_project_1_compiler.srr 6887 2018-07-02
DBSTAR_RGMII\par\fpga_project_1\impl\synthesize\rev_1\synlog\fpga_project_1_compiler.srr.db 8192 2018-07-02
DBSTAR_RGMII\par\fpga_project_1\impl\synthesize\rev_1\synlog\fpga_project_1_compiler.srr.rptmap 78 2018-07-02
DBSTAR_RGMII\par\fpga_project_1\impl\synthesize\rev_1\synlog\fpga_project_1_fpga_mapper.srr 71291 2018-07-02
DBSTAR_RGMII\par\fpga_project_1\impl\synthesize\rev_1\synlog\fpga_project_1_fpga_mapper.srr.db 8192 2018-07-02
DBSTAR_RGMII\par\fpga_project_1\impl\synthesize\rev_1\synlog\fpga_project_1_fpga_mapper.szr 25276 2018-07-02
DBSTAR_RGMII\par\fpga_project_1\impl\synthesize\rev_1\synlog\fpga_project_1_fpga_mapper.xck 303 2018-03-29
DBSTAR_RGMII\par\fpga_project_1\impl\synthesize\rev_1\synlog\fpga_project_1_multi_srs_gen.srr 1531 2018-07-02
DBSTAR_RGMII\par\fpga_project_1\impl\synthesize\rev_1\synlog\fpga_project_1_multi_srs_gen.srr.db 8192 2018-07-02
DBSTAR_RGMII\par\fpga_project_1\impl\synthesize\rev_1\synlog\fpga_project_1_premap.srr 8885 2018-07-02
DBSTAR_RGMII\par\fpga_project_1\impl\synthesize\rev_1\synlog\fpga_project_1_premap.srr.db 8192 2018-07-02
DBSTAR_RGMII\par\fpga_project_1\impl\synthesize\rev_1\synlog\fpga_project_1_premap.szr 13450 2018-07-02
DBSTAR_RGMII\par\fpga_project_1\impl\synthesize\rev_1\synlog\fpga_project_1_premap.xck 289 2018-07-02
DBSTAR_RGMII\par\fpga_project_1\impl\synthesize\rev_1\synlog\hierarea.rpt.rptmap 55 2018-07-02
DBSTAR_RGMII\par\fpga_project_1\impl\synthesize\rev_1\synlog\incr_compile.rpt.rptmap 72 2018-07-02
DBSTAR_RGMII\par\fpga_project_1\impl\synthesize\rev_1\synlog\layer0.tlg.rptmap 139 2018-07-02
DBSTAR_RGMII\par\fpga_project_1\impl\synthesize\rev_1\synlog\report\fpga_project_1_compiler_errors.txt 117 2018-03-29
DBSTAR_RGMII\par\fpga_project_1\impl\synthesize\rev_1\synlog\report\fpga_project_1_compiler_notes.txt 1732 2018-07-02
DBSTAR_RGMII\par\fpga_project_1\impl\synthesize\rev_1\synlog\report\fpga_project_1_compiler_runstatus.xml 1668 2018-07-02
DBSTAR_RGMII\par\fpga_project_1\impl\synthesize\rev_1\synlog\report\fpga_project_1_compiler_warnings.txt 1466 2018-07-02
DBSTAR_RGMII\par\fpga_project_1\impl\synthesize\rev_1\synlog\report\fpga_project_1_fpga_mapper_area_report.xml 1388 2018-07-02
DBSTAR_RGMII\par\fpga_project_1\impl\synthesize\rev_1\synlog\report\fpga_project_1_fpga_mapper_combined_clk.rpt 2093 2018-03-29
DBSTAR_RGMII\par\fpga_project_1\impl\synthesize\rev_1\synlog\report\fpga_project_1_fpga_mapper_errors.txt 0 2018-07-02
DBSTAR_RGMII\par\fpga_project_1\impl\synthesize\rev_1\synlog\report\fpga_project_1_fpga_mapper_notes.txt 2924 2018-07-02
DBSTAR_RGMII\par\fpga_project_1\impl\synthesize\rev_1\synlog\report\fpga_project_1_fpga_mapper_opt_report.xml 435 2018-07-02
DBSTAR_RGMII\par\fpga_project_1\impl\synthesize\rev_1\synlog\report\fpga_project_1_fpga_mapper_resourceusage.rpt 691 2018-07-02
DBSTAR_RGMII\par\fpga_project_1\impl\synthesize\rev_1\synlog\report\fpga_project_1_fpga_mapper_runstatus.xml 1595 2018-07-02
DBSTAR_RGMII\par\fpga_project_1\impl\synthesize\rev_1\synlog\report\fpga_project_1_fpga_mapper_timing_report.xml 1156 2018-07-02
DBSTAR_RGMII\par\fpga_project_1\impl\synthesize\rev_1\synlog\report\fpga_project_1_fpga_mapper_warnings.txt 621 2018-07-02
DBSTAR_RGMII\par\fpga_project_1\impl\synthesize\rev_1\synlog\report\fpga_project_1_premap_combined_clk.rpt 1795 2018-07-02
DBSTAR_RGMII\par\fpga_project_1\impl\synthesize\rev_1\synlog\report\fpga_project_1_premap_errors.txt 0 2018-07-02
DBSTAR_RGMII\par\fpga_project_1\impl\synthesize\rev_1\synlog\report\fpga_project_1_premap_notes.txt 562 2018-07-02
DBSTAR_RGMII\par\fpga_project_1\impl\synthesize\rev_1\synlog\report\fpga_project_1_premap_runstatus.xml 1574 2018-07-02
DBSTAR_RGMII\par\fpga_project_1\impl\synthesize\rev_1\synlog\report\fpga_project_1_premap_warnings.txt 1168 2018-07-02
DBSTAR_RGMII\par\fpga_project_1\impl\synthesize\rev_1\synlog\report\metrics.db 45056 2018-07-02
DBSTAR_RGMII\par\fpga_project_1\impl\synthesize\rev_1\synlog\syntax_constraint_check.rpt.rptmap 86 2018-07-02
DBSTAR_RGMII\par\fpga_project_1\impl\synthesize\rev_1\syntmp\closed.png 3672 2017-11-29
DBSTAR_RGMII\par\fpga_project_1\impl\synthesize\rev_1\syntmp\cmdrec_compiler.log 2618 2018-07-02
DBSTAR_RGMII\par\fpga_project_1\impl\synthesize\rev_1\syntmp\cmdrec_fpga_mapper.log 3466 2018-07-02
DBSTAR_RGMII\par\fpga_project_1\impl\synthesize\rev_1\syntmp\cmdrec_multi_srs_gen.log 1040 2018-07-02
DBSTAR_RGMII\par\fpga_project_1\impl\synthesize\rev_1\syntmp\cmdrec_premap.log 3368 2018-07-02
DBSTAR_RGMII\par\fpga_project_1\impl\synthesize\rev_1\syntmp\fpga_project_1.plg 977 2018-07-02
DBSTAR_RGMII\par\fpga_project_1\impl\synthesize\rev_1\syntmp\fpga_project_1_fpga_mapper_srr.htm 74795 2018-07-02
DBSTAR_RGMII\par\fpga_project_1\impl\synthesize\rev_1\syntmp\fpga_project_1_fpga_mapper_toc.htm 5636 2018-07-02
DBSTAR_RGMII\par\fpga_project_1\impl\synthesize\rev_1\syntmp\fpga_project_1_multi_srs_gen_srr.htm 1842 2018-07-02
DBSTAR_RGMII\par\fpga_project_1\impl\synthesize\rev_1\syntmp\fpga_project_1_multi_srs_gen_toc.htm 1540 2018-07-02
DBSTAR_RGMII\par\fpga_project_1\impl\synthesize\rev_1\syntmp\fpga_project_1_premap_srr.htm 10610 2018-07-02
DBSTAR_RGMII\par\fpga_project_1\impl\synthesize\rev_1\syntmp\fpga_project_1_premap_toc.htm 1932 2018-07-02
DBSTAR_RGMII\par\fpga_project_1\impl\synthesize\rev_1\syntmp\fpga_project_1_srr.htm 11034 2018-07-02
DBSTAR_RGMII\par\fpga_project_1\impl\synthesize\rev_1\syntmp\fpga_project_1_toc.htm 6681 2018-07-02
DBSTAR_RGMII\par\fpga_project_1\impl\synthesize\rev_1\syntmp\open.png 452 2017-11-29
DBSTAR_RGMII\par\fpga_project_1\impl\synthesize\rev_1\syntmp\run_option.xml 1308 2018-07-02
DBSTAR_RGMII\par\fpga_project_1\impl\synthesize\rev_1\syntmp\statusReport.html 4745 2018-07-02

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