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文件名称:an487_design_example

  • 所属分类：
    VHDL编程
  • 标签属性：
    [VHDL] [源码]
  • 上传时间：
    2008-10-13
  • 文件大小：
    589.28kb
  • 已下载：
    2次
  • 提 供 者：
    zhiq****
  • 相关连接：
    无
  • 下载说明：
    别用迅雷下载，失败请重下，重下不扣分！
修正介绍说明

介绍说明－－下载内容来自于网络，使用问题请自行百度

用verlog hdl开发的SPI 的源码
(系统自动生成,下载前可以参看下载内容)

下载文件列表

SPI_to_I2S_Altera_MAX_II_CPLD_Design_Example/
SPI_to_I2S_Altera_MAX_II_CPLD_Design_Example/code/
SPI_to_I2S_Altera_MAX_II_CPLD_Design_Example/code/spi_to_i2s.v
SPI_to_I2S_Altera_MAX_II_CPLD_Design_Example/modelsim/
SPI_to_I2S_Altera_MAX_II_CPLD_Design_Example/modelsim/spi_to_i2s.cr.mti
SPI_to_I2S_Altera_MAX_II_CPLD_Design_Example/modelsim/spi_to_i2s.mpf
SPI_to_I2S_Altera_MAX_II_CPLD_Design_Example/modelsim/spi_to_i2s.v
SPI_to_I2S_Altera_MAX_II_CPLD_Design_Example/modelsim/SPI_to_I2S_test.v
SPI_to_I2S_Altera_MAX_II_CPLD_Design_Example/modelsim/vsim.wlf
SPI_to_I2S_Altera_MAX_II_CPLD_Design_Example/modelsim/wave.bmp
SPI_to_I2S_Altera_MAX_II_CPLD_Design_Example/modelsim/wave.do
SPI_to_I2S_Altera_MAX_II_CPLD_Design_Example/modelsim/work/
SPI_to_I2S_Altera_MAX_II_CPLD_Design_Example/modelsim/work/@s@p@i_to_@i2@s_test/
SPI_to_I2S_Altera_MAX_II_CPLD_Design_Example/modelsim/work/@s@p@i_to_@i2@s_test/verilog.psm
SPI_to_I2S_Altera_MAX_II_CPLD_Design_Example/modelsim/work/@s@p@i_to_@i2@s_test/_primary.dat
SPI_to_I2S_Altera_MAX_II_CPLD_Design_Example/modelsim/work/@s@p@i_to_@i2@s_test/_primary.vhd
SPI_to_I2S_Altera_MAX_II_CPLD_Design_Example/modelsim/work/i2s_master/
SPI_to_I2S_Altera_MAX_II_CPLD_Design_Example/modelsim/work/i2s_master/verilog.psm
SPI_to_I2S_Altera_MAX_II_CPLD_Design_Example/modelsim/work/i2s_master/_primary.dat
SPI_to_I2S_Altera_MAX_II_CPLD_Design_Example/modelsim/work/i2s_master/_primary.vhd
SPI_to_I2S_Altera_MAX_II_CPLD_Design_Example/modelsim/work/spi_slave/
SPI_to_I2S_Altera_MAX_II_CPLD_Design_Example/modelsim/work/spi_slave/verilog.psm
SPI_to_I2S_Altera_MAX_II_CPLD_Design_Example/modelsim/work/spi_slave/_primary.dat
SPI_to_I2S_Altera_MAX_II_CPLD_Design_Example/modelsim/work/spi_slave/_primary.vhd
SPI_to_I2S_Altera_MAX_II_CPLD_Design_Example/modelsim/work/spi_to_i2s/
SPI_to_I2S_Altera_MAX_II_CPLD_Design_Example/modelsim/work/spi_to_i2s/verilog.psm
SPI_to_I2S_Altera_MAX_II_CPLD_Design_Example/modelsim/work/spi_to_i2s/_primary.dat
SPI_to_I2S_Altera_MAX_II_CPLD_Design_Example/modelsim/work/spi_to_i2s/_primary.vhd
SPI_to_I2S_Altera_MAX_II_CPLD_Design_Example/modelsim/work/_info
SPI_to_I2S_Altera_MAX_II_CPLD_Design_Example/quartus/
SPI_to_I2S_Altera_MAX_II_CPLD_Design_Example/quartus/db/
SPI_to_I2S_Altera_MAX_II_CPLD_Design_Example/quartus/db/spi_to_i2s.(0).cnf.cdb
SPI_to_I2S_Altera_MAX_II_CPLD_Design_Example/quartus/db/spi_to_i2s.(0).cnf.hdb
SPI_to_I2S_Altera_MAX_II_CPLD_Design_Example/quartus/db/spi_to_i2s.(1).cnf.cdb
SPI_to_I2S_Altera_MAX_II_CPLD_Design_Example/quartus/db/spi_to_i2s.(1).cnf.hdb
SPI_to_I2S_Altera_MAX_II_CPLD_Design_Example/quartus/db/spi_to_i2s.(2).cnf.cdb
SPI_to_I2S_Altera_MAX_II_CPLD_Design_Example/quartus/db/spi_to_i2s.(2).cnf.hdb
SPI_to_I2S_Altera_MAX_II_CPLD_Design_Example/quartus/db/spi_to_i2s.asm.qmsg
SPI_to_I2S_Altera_MAX_II_CPLD_Design_Example/quartus/db/spi_to_i2s.asm_labs.ddb
SPI_to_I2S_Altera_MAX_II_CPLD_Design_Example/quartus/db/spi_to_i2s.cbx.xml
SPI_to_I2S_Altera_MAX_II_CPLD_Design_Example/quartus/db/spi_to_i2s.cmp.cdb
SPI_to_I2S_Altera_MAX_II_CPLD_Design_Example/quartus/db/spi_to_i2s.cmp.hdb
SPI_to_I2S_Altera_MAX_II_CPLD_Design_Example/quartus/db/spi_to_i2s.cmp.logdb
SPI_to_I2S_Altera_MAX_II_CPLD_Design_Example/quartus/db/spi_to_i2s.cmp.rdb
SPI_to_I2S_Altera_MAX_II_CPLD_Design_Example/quartus/db/spi_to_i2s.cmp.tdb
SPI_to_I2S_Altera_MAX_II_CPLD_Design_Example/quartus/db/spi_to_i2s.cmp0.ddb
SPI_to_I2S_Altera_MAX_II_CPLD_Design_Example/quartus/db/spi_to_i2s.dbp
SPI_to_I2S_Altera_MAX_II_CPLD_Design_Example/quartus/db/spi_to_i2s.db_info
SPI_to_I2S_Altera_MAX_II_CPLD_Design_Example/quartus/db/spi_to_i2s.eco.cdb
SPI_to_I2S_Altera_MAX_II_CPLD_Design_Example/quartus/db/spi_to_i2s.fit.qmsg
SPI_to_I2S_Altera_MAX_II_CPLD_Design_Example/quartus/db/spi_to_i2s.hier_info
SPI_to_I2S_Altera_MAX_II_CPLD_Design_Example/quartus/db/spi_to_i2s.hif
SPI_to_I2S_Altera_MAX_II_CPLD_Design_Example/quartus/db/spi_to_i2s.map.cdb
SPI_to_I2S_Altera_MAX_II_CPLD_Design_Example/quartus/db/spi_to_i2s.map.hdb
SPI_to_I2S_Altera_MAX_II_CPLD_Design_Example/quartus/db/spi_to_i2s.map.logdb
SPI_to_I2S_Altera_MAX_II_CPLD_Design_Example/quartus/db/spi_to_i2s.map.qmsg
SPI_to_I2S_Altera_MAX_II_CPLD_Design_Example/quartus/db/spi_to_i2s.pre_map.cdb
SPI_to_I2S_Altera_MAX_II_CPLD_Design_Example/quartus/db/spi_to_i2s.pre_map.hdb
SPI_to_I2S_Altera_MAX_II_CPLD_Design_Example/quartus/db/spi_to_i2s.psp
SPI_to_I2S_Altera_MAX_II_CPLD_Design_Example/quartus/db/spi_to_i2s.pss
SPI_to_I2S_Altera_MAX_II_CPLD_Design_Example/quartus/db/spi_to_i2s.rtlv.hdb
SPI_to_I2S_Altera_MAX_II_CPLD_Design_Example/quartus/db/spi_to_i2s.rtlv_sg.cdb
SPI_to_I2S_Altera_MAX_II_CPLD_Design_Example/quartus/db/spi_to_i2s.rtlv_sg_swap.cdb
SPI_to_I2S_Altera_MAX_II_CPLD_Design_Example/quartus/db/spi_to_i2s.sgdiff.cdb
SPI_to_I2S_Altera_MAX_II_CPLD_Design_Example/quartus/db/spi_to_i2s.sgdiff.hdb
SPI_to_I2S_Altera_MAX_II_CPLD_Design_Example/quartus/db/spi_to_i2s.signalprobe.cdb
SPI_to_I2S_Altera_MAX_II_CPLD_Design_Example/quartus/db/spi_to_i2s.sld_design_entry.sci
SPI_to_I2S_Altera_MAX_II_CPLD_Design_Example/quartus/db/spi_to_i2s.sld_design_entry_dsc.sci
SPI_to_I2S_Altera_MAX_II_

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