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文件名称:Xil3SD1800A_MIG_ISIM_vlog_v92

  • 所属分类：
    VHDL编程
  • 标签属性：
    [PDF]
  • 上传时间：
    2008-10-13
  • 文件大小：
    3.23mb
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Xilinx DDR2存储器接口调试代码，主频167Mhz，嵌入了CHIPSCORP代码。
(系统自动生成,下载前可以参看下载内容)

下载文件列表

Xil3SD1800A_MIG_ISIM_vlog_v92/
Xil3SD1800A_MIG_ISIM_vlog_v92.pdf
Xil3SD1800A_MIG_ISIM_vlog_v92/ddr2_32Mx32_vlog/
Xil3SD1800A_MIG_ISIM_vlog_v92/ddr2_32Mx32_vlog/ddr2_32Mx32/
Xil3SD1800A_MIG_ISIM_vlog_v92/ddr2_32Mx32_vlog/ddr2_32Mx32.veo
Xil3SD1800A_MIG_ISIM_vlog_v92/ddr2_32Mx32_vlog/ddr2_32Mx32.xco
Xil3SD1800A_MIG_ISIM_vlog_v92/ddr2_32Mx32_vlog/ddr2_32Mx32/docs/
Xil3SD1800A_MIG_ISIM_vlog_v92/ddr2_32Mx32_vlog/ddr2_32Mx32/docs/adr_cntrl_timing_0.xls
Xil3SD1800A_MIG_ISIM_vlog_v92/ddr2_32Mx32_vlog/ddr2_32Mx32/docs/read_data_timing_0.xls
Xil3SD1800A_MIG_ISIM_vlog_v92/ddr2_32Mx32_vlog/ddr2_32Mx32/docs/write_data_timing_0.xls
Xil3SD1800A_MIG_ISIM_vlog_v92/ddr2_32Mx32_vlog/ddr2_32Mx32/docs/xapp454_sp3.url
Xil3SD1800A_MIG_ISIM_vlog_v92/ddr2_32Mx32_vlog/ddr2_32Mx32/example_design/
Xil3SD1800A_MIG_ISIM_vlog_v92/ddr2_32Mx32_vlog/ddr2_32Mx32/example_design/datasheet.txt
Xil3SD1800A_MIG_ISIM_vlog_v92/ddr2_32Mx32_vlog/ddr2_32Mx32/example_design/log.txt
Xil3SD1800A_MIG_ISIM_vlog_v92/ddr2_32Mx32_vlog/ddr2_32Mx32/example_design/mig.prj
Xil3SD1800A_MIG_ISIM_vlog_v92/ddr2_32Mx32_vlog/ddr2_32Mx32/example_design/par/
Xil3SD1800A_MIG_ISIM_vlog_v92/ddr2_32Mx32_vlog/ddr2_32Mx32/example_design/par/automake.log
Xil3SD1800A_MIG_ISIM_vlog_v92/ddr2_32Mx32_vlog/ddr2_32Mx32/example_design/par/create_ise.bat
Xil3SD1800A_MIG_ISIM_vlog_v92/ddr2_32Mx32_vlog/ddr2_32Mx32/example_design/par/ddr2_32Mx32.ucf
Xil3SD1800A_MIG_ISIM_vlog_v92/ddr2_32Mx32_vlog/ddr2_32Mx32/example_design/par/ddr2_32Mx32_summary.html
Xil3SD1800A_MIG_ISIM_vlog_v92/ddr2_32Mx32_vlog/ddr2_32Mx32/example_design/par/ddr2_speedway.bat
Xil3SD1800A_MIG_ISIM_vlog_v92/ddr2_32Mx32_vlog/ddr2_32Mx32/example_design/par/ddr2_speedway.ise
Xil3SD1800A_MIG_ISIM_vlog_v92/ddr2_32Mx32_vlog/ddr2_32Mx32/example_design/par/ddr2_speedway.ise_ISE_Backup
Xil3SD1800A_MIG_ISIM_vlog_v92/ddr2_32Mx32_vlog/ddr2_32Mx32/example_design/par/ddr2_speedway.restore
Xil3SD1800A_MIG_ISIM_vlog_v92/ddr2_32Mx32_vlog/ddr2_32Mx32/example_design/par/example.xwv
Xil3SD1800A_MIG_ISIM_vlog_v92/ddr2_32Mx32_vlog/ddr2_32Mx32/example_design/par/ise_flow.bat
Xil3SD1800A_MIG_ISIM_vlog_v92/ddr2_32Mx32_vlog/ddr2_32Mx32/example_design/par/ise_run.txt
Xil3SD1800A_MIG_ISIM_vlog_v92/ddr2_32Mx32_vlog/ddr2_32Mx32/example_design/par/isim/
Xil3SD1800A_MIG_ISIM_vlog_v92/ddr2_32Mx32_vlog/ddr2_32Mx32/example_design/par/isim.cmd
Xil3SD1800A_MIG_ISIM_vlog_v92/ddr2_32Mx32_vlog/ddr2_32Mx32/example_design/par/isim.hdlsourcefiles
Xil3SD1800A_MIG_ISIM_vlog_v92/ddr2_32Mx32_vlog/ddr2_32Mx32/example_design/par/isim.log
Xil3SD1800A_MIG_ISIM_vlog_v92/ddr2_32Mx32_vlog/ddr2_32Mx32/example_design/par/isim.tmp_save/
Xil3SD1800A_MIG_ISIM_vlog_v92/ddr2_32Mx32_vlog/ddr2_32Mx32/example_design/par/isim.tmp_save/_1
Xil3SD1800A_MIG_ISIM_vlog_v92/ddr2_32Mx32_vlog/ddr2_32Mx32/example_design/par/isimwavedata.xwv
Xil3SD1800A_MIG_ISIM_vlog_v92/ddr2_32Mx32_vlog/ddr2_32Mx32/example_design/par/isim/temp/
Xil3SD1800A_MIG_ISIM_vlog_v92/ddr2_32Mx32_vlog/ddr2_32Mx32/example_design/par/isim/temp/hdllib.ref
Xil3SD1800A_MIG_ISIM_vlog_v92/ddr2_32Mx32_vlog/ddr2_32Mx32/example_design/par/isim/temp/hdpdeps.ref
Xil3SD1800A_MIG_ISIM_vlog_v92/ddr2_32Mx32_vlog/ddr2_32Mx32/example_design/par/isim/temp/vlg02/
Xil3SD1800A_MIG_ISIM_vlog_v92/ddr2_32Mx32_vlog/ddr2_32Mx32/example_design/par/isim/temp/vlg02/ddr2__32_mx32__infrastructure.bin
Xil3SD1800A_MIG_ISIM_vlog_v92/ddr2_32Mx32_vlog/ddr2_32Mx32/example_design/par/isim/temp/vlg0D/
Xil3SD1800A_MIG_ISIM_vlog_v92/ddr2_32Mx32_vlog/ddr2_32Mx32/example_design/par/isim/temp/vlg0D/ddr2__32_mx32__infrastructure__iobs__0.bin
Xil3SD1800A_MIG_ISIM_vlog_v92/ddr2_32Mx32_vlog/ddr2_32Mx32/example_design/par/isim/temp/vlg0F/
Xil3SD1800A_MIG_ISIM_vlog_v92/ddr2_32Mx32_vlog/ddr2_32Mx32/example_design/par/isim/temp/vlg0F/ddr2__32_mx32__dqs__delay.bin
Xil3SD1800A_MIG_ISIM_vlog_v92/ddr2_32Mx32_vlog/ddr2_32Mx32/example_design/par/isim/temp/vlg10/
Xil3SD1800A_MIG_ISIM_vlog_v92/ddr2_32Mx32_vlog/ddr2_32Mx32/example_design/par/isim/temp/vlg10/ddr2__32_mx32__controller__iobs__0.bin
Xil3SD1800A_MIG_ISIM_vlog_v92/ddr2_32Mx32_vlog/ddr2_32Mx32/example_design/par/isim/temp/vlg14/
Xil3SD1800A_MIG_ISIM_vlog_v92/ddr2_32Mx32_vlog/ddr2_32Mx32/example_design/par/isim/temp/vlg14/ddr2__32_mx32__controller__0.bin
Xil3SD1800A_MIG_ISIM_vlog_v92/ddr2_32Mx32_vlog/ddr2_32Mx32/example_design/par/isim/temp/vlg18/
Xil3SD1800A_MIG_ISIM_vlog_v92/ddr2_32Mx32_vlog/ddr2_32Mx32/example_design/par/isim/temp/vlg18/ddr2__32_mx32__addr__gen__0.bin
Xil3SD1800A_MIG_ISIM_vlog_v92/ddr2_32Mx32_vlog/ddr2_32Mx32/example_design/par/isim/temp/vlg19/
Xil3SD1800A_MIG_ISIM_vlog_v92/ddr2_32Mx32_vlog/ddr2_32Mx32/example_design/par/isim/temp/vlg19/ddr2__32_mx32__fifo__0__wr__en__0.bin
Xil3SD1800A_MIG_ISIM_vlog_v92/ddr2_32Mx32_vlog/ddr2_32Mx32/example_design/par/isim/temp/vlg1B/
Xil3SD1800A_MIG_ISIM_vlog_v92/ddr2_32Mx32_vlog/ddr2_32Mx32/example_design/par/isim/temp/vlg1B/ddr2__32_mx32__cal__ctl.bin
Xil3SD1800A_MIG_ISIM_vlog_v92/ddr2_32Mx32_vlog/ddr2_32Mx32/example_design/par/isim/temp/vlg2B/
Xil3SD1800A_MIG_ISIM_vlog_v92/ddr2_32Mx32_vlog/ddr2_32Mx32/example_design/par/isim/temp/vlg2B/ddr2__32_mx32__top__0.bin
Xil3SD180

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