it6505官方编程指南。
Reset IT6505
Following steps are the reset procedure of IT6505.
1. reg05 ← 0x3B to enable reference domain clock and reset all the other register.
2. Delay 1 millisecond.
3. reg05 ← 0x1F to reset reference clock, and reset all register to the default value.
4. reg61[1] ← ‘1’ to reset TxFIFO.
5. reg5C←0x02. reg15[1][0] ← ‘11’ then ← ‘01’
to reset PHY FIFO.
7. reg59[0] ← ‘1’
8. reg5A[2][0] ← ‘0’ ‘1’
9. Set regCB to enable aux defer and I2C read step.
10. Reg5f[2:0] ← ‘110’Reg0C ← 0x08 for set the interrupt pin as active low and open-drain.
12. Write reg06/reg07/reg08 bits for clearing monitor status bit to start monitor events.
13. Write reg09/reg0A/reg0B bits for enabling interrupt by events. Bit value ‘1’ is for enabling the
interrupt, and ‘0’ is for disabling.
14. Reg15[0] ← ‘1’ if need to inverse QCLK, otherwise do not need.Reg12[4] ← ‘1’ to inverse video
input PCLK.reg11←0x01
17. reg20← 0x28
18. reg3A[2] ← ‘1’If disable scrambling, reg5f[5] ← ‘1’,
otherwise reg5F[5] ← ‘0’
20. Set reg16 for enabling SSC, LBR mode and lane enable.
21. if LBR enabling, reg5C[1] ← ‘0’, else reg5C[1] ← ‘1’
22. if enable one lane, reg5C[7:4][0] ← ‘0001’ ‘1’
if enable two lanes, reg5C[7:4][0] ← ‘0011’ ‘1’
if enable four lanes, reg5C[7:4][0] ← ‘1111’ ‘1’
23. If enable SSC, regD4[5:4] ← ‘01’, otherwise regD4[5:4] ← ‘00’
24. If enhance framing, regD3 ← 0x33, otherwise regD3 ← 0x32.
25. Adjust the internal state into initial state.