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文件名称:AT510-MN-80001-r2p0-00rel0

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  • 上传时间:
    2019-11-08
  • 文件大小:
    4.15mb
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    8次
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    别用迅雷下载,失败请重下,重下不扣分!

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ORTEX-M0 processor officially open source code package!The newest version.
相关搜索: cortex-m0

(系统自动生成,下载前可以参看下载内容)

下载文件列表

文件名大小更新时间
AT510-MN-80001-r2p0-00rel0\ARM_Cortex_M0_DesignStart_Eval_r2p0-00rel0_Release_Note.pdf 914945 2017-10-02
AT510-MN-80001-r2p0-00rel0\cores\cortexm0_designstart_r2p0\logical\cortexm0_integration\verilog\cortexm0ds_logic.v 796360 2017-10-02
AT510-MN-80001-r2p0-00rel0\cores\cortexm0_designstart_r2p0\logical\cortexm0_integration\verilog\CORTEXM0INTEGRATION.v 8389 2017-10-02
AT510-MN-80001-r2p0-00rel0\documentation\arm_cortex_m0_designstart_eval_fpga_user_guide.pdf 586888 2017-10-03
AT510-MN-80001-r2p0-00rel0\documentation\arm_cortex_m0_designstart_eval_user_guide.pdf 533570 2017-10-03
AT510-MN-80001-r2p0-00rel0\logical\cmsdk_ahb_bitband\verilog\cmsdk_ahb_bitband.v 41516 2017-10-02
AT510-MN-80001-r2p0-00rel0\logical\cmsdk_ahb_busmatrix\bin\BuildBusMatrix.pl 83973 2017-10-02
AT510-MN-80001-r2p0-00rel0\logical\cmsdk_ahb_busmatrix\bin\lib\xmlparser.pm 46625 2017-10-02
AT510-MN-80001-r2p0-00rel0\logical\cmsdk_ahb_busmatrix\README.txt 2650 2017-10-02
AT510-MN-80001-r2p0-00rel0\logical\cmsdk_ahb_busmatrix\verilog\src\cmsdk_ahb_bm_burst_arb.v 12416 2017-10-02
AT510-MN-80001-r2p0-00rel0\logical\cmsdk_ahb_busmatrix\verilog\src\cmsdk_ahb_bm_decode.v 22054 2017-10-02
AT510-MN-80001-r2p0-00rel0\logical\cmsdk_ahb_busmatrix\verilog\src\cmsdk_ahb_bm_default_slave.v 4978 2017-10-02
AT510-MN-80001-r2p0-00rel0\logical\cmsdk_ahb_busmatrix\verilog\src\cmsdk_ahb_bm_fixed_arb.v 7321 2017-10-02
AT510-MN-80001-r2p0-00rel0\logical\cmsdk_ahb_busmatrix\verilog\src\cmsdk_ahb_bm_input_stage.v 23321 2017-10-02
AT510-MN-80001-r2p0-00rel0\logical\cmsdk_ahb_busmatrix\verilog\src\cmsdk_ahb_bm_output_stage.v 24091 2017-10-02
AT510-MN-80001-r2p0-00rel0\logical\cmsdk_ahb_busmatrix\verilog\src\cmsdk_ahb_bm_round_arb.v 14849 2017-10-02
AT510-MN-80001-r2p0-00rel0\logical\cmsdk_ahb_busmatrix\verilog\src\cmsdk_ahb_bm_single_arb.v 6794 2017-10-02
AT510-MN-80001-r2p0-00rel0\logical\cmsdk_ahb_busmatrix\verilog\src\cmsdk_ahb_bm_single_output_stage.v 20063 2017-10-02
AT510-MN-80001-r2p0-00rel0\logical\cmsdk_ahb_busmatrix\verilog\src\cmsdk_ahb_busmatrix.v 25776 2017-10-02
AT510-MN-80001-r2p0-00rel0\logical\cmsdk_ahb_busmatrix\verilog\src\cmsdk_ahb_busmatrix_lite.v 15731 2017-10-02
AT510-MN-80001-r2p0-00rel0\logical\cmsdk_ahb_busmatrix\verilog\src\cmsdk_ahb_busmatrix_spirit.xml 22057 2017-10-02
AT510-MN-80001-r2p0-00rel0\logical\cmsdk_ahb_busmatrix\xml\example2x3_full.xml 4509 2017-10-02
AT510-MN-80001-r2p0-00rel0\logical\cmsdk_ahb_busmatrix\xml\example2x3_sparse.xml 4254 2017-10-02
AT510-MN-80001-r2p0-00rel0\logical\cmsdk_ahb_default_slave\verilog\cmsdk_ahb_default_slave.v 4409 2017-10-02
AT510-MN-80001-r2p0-00rel0\logical\cmsdk_ahb_downsizer64\verilog\cmsdk_ahb_downsizer64.v 40972 2017-10-02
AT510-MN-80001-r2p0-00rel0\logical\cmsdk_ahb_eg_slave\verilog\cmsdk_ahb_eg_slave.v 5221 2017-10-02
AT510-MN-80001-r2p0-00rel0\logical\cmsdk_ahb_eg_slave\verilog\cmsdk_ahb_eg_slave_interface.v 6445 2017-10-02
AT510-MN-80001-r2p0-00rel0\logical\cmsdk_ahb_eg_slave\verilog\cmsdk_ahb_eg_slave_reg.v 8448 2017-10-02
AT510-MN-80001-r2p0-00rel0\logical\cmsdk_ahb_fileread_masters\bin\fm2conv.pl 90842 2017-10-02
AT510-MN-80001-r2p0-00rel0\logical\cmsdk_ahb_fileread_masters\example\frbm_example.fri 13410 2017-10-02
AT510-MN-80001-r2p0-00rel0\logical\cmsdk_ahb_fileread_masters\example\makefile 4718 2017-10-02
AT510-MN-80001-r2p0-00rel0\logical\cmsdk_ahb_fileread_masters\example\tbench.vc 1605 2017-10-02
AT510-MN-80001-r2p0-00rel0\logical\cmsdk_ahb_fileread_masters\example\tb_frbm_example.v 7809 2017-10-02
AT510-MN-80001-r2p0-00rel0\logical\cmsdk_ahb_fileread_masters\verilog\cmsdk_ahb_filereadcore.v 64523 2017-10-02
AT510-MN-80001-r2p0-00rel0\logical\cmsdk_ahb_fileread_masters\verilog\cmsdk_ahb_fileread_funnel.v 3526 2017-10-02
AT510-MN-80001-r2p0-00rel0\logical\cmsdk_ahb_fileread_masters\verilog\cmsdk_ahb_fileread_master32.v 5442 2017-10-02
AT510-MN-80001-r2p0-00rel0\logical\cmsdk_ahb_fileread_masters\verilog\cmsdk_ahb_fileread_master64.v 4711 2017-10-02
AT510-MN-80001-r2p0-00rel0\logical\cmsdk_ahb_gpio\verilog\cmsdk_ahb_gpio.v 5302 2017-10-02
AT510-MN-80001-r2p0-00rel0\logical\cmsdk_ahb_gpio\verilog\cmsdk_ahb_to_iop.v 3831 2017-10-02
AT510-MN-80001-r2p0-00rel0\logical\cmsdk_ahb_master_mux\verilog\cmsdk_ahb_master_mux.v 34357 2017-10-02
AT510-MN-80001-r2p0-00rel0\logical\cmsdk_ahb_slave_mux\verilog\cmsdk_ahb_slave_mux.v 9712 2017-10-02
AT510-MN-80001-r2p0-00rel0\logical\cmsdk_ahb_timeout_mon\verilog\cmsdk_ahb_timeout_mon.v 12076 2017-10-02
AT510-MN-80001-r2p0-00rel0\logical\cmsdk_ahb_to_ahb_apb_async\verilog\cmsdk_ahb_to_ahb_apb_async.v 27795 2017-10-02
AT510-MN-80001-r2p0-00rel0\logical\cmsdk_ahb_to_ahb_apb_async\verilog\cmsdk_ahb_to_ahb_apb_async_launch.v 2075 2017-10-02
AT510-MN-80001-r2p0-00rel0\logical\cmsdk_ahb_to_ahb_apb_async\verilog\cmsdk_ahb_to_ahb_apb_async_master.v 10010 2017-10-02
AT510-MN-80001-r2p0-00rel0\logical\cmsdk_ahb_to_ahb_apb_async\verilog\cmsdk_ahb_to_ahb_apb_async_sample_and_hold.v 2175 2017-10-02
AT510-MN-80001-r2p0-00rel0\logical\cmsdk_ahb_to_ahb_apb_async\verilog\cmsdk_ahb_to_ahb_apb_async_slave.v 9099 2017-10-02
AT510-MN-80001-r2p0-00rel0\logical\cmsdk_ahb_to_ahb_apb_async\verilog\cmsdk_ahb_to_ahb_apb_async_synchronizer.v 1610 2017-10-02
AT510-MN-80001-r2p0-00rel0\logical\cmsdk_ahb_to_ahb_sync\verilog\cmsdk_ahb_to_ahb_sync.v 25826 2017-10-02
AT510-MN-80001-r2p0-00rel0\logical\cmsdk_ahb_to_ahb_sync_down\verilog\cmsdk_ahb_to_ahb_sync_down.v 10009 2017-10-02
AT510-MN-80001-r2p0-00rel0\logical\cmsdk_ahb_to_ahb_sync_down\verilog\cmsdk_ahb_to_ahb_sync_down_core.v 36507 2017-10-02
AT510-MN-80001-r2p0-00rel0\logical\cmsdk_ahb_to_ahb_sync_down\verilog\cmsdk_ahb_to_ahb_sync_error_canc.v 11465 2017-10-02
AT510-MN-80001-r2p0-00rel0\logical\cmsdk_ahb_to_ahb_sync_down\verilog\cmsdk_ahb_to_ahb_sync_wb.v 33436 2017-10-02
AT510-MN-80001-r2p0-00rel0\logical\cmsdk_ahb_to_ahb_sync_up\verilog\cmsdk_ahb_to_ahb_sync_up.v 9954 2017-10-02
AT510-MN-80001-r2p0-00rel0\logical\cmsdk_ahb_to_ahb_sync_up\verilog\cmsdk_ahb_to_ahb_sync_up_core.v 52627 2017-10-02
AT510-MN-80001-r2p0-00rel0\logical\cmsdk_ahb_to_apb\verilog\cmsdk_ahb_to_apb.v 16755 2017-10-02
AT510-MN-80001-r2p0-00rel0\logical\cmsdk_ahb_to_apb_async\verilog\cmsdk_ahb_to_apb_async.v 12846 2017-10-02
AT510-MN-80001-r2p0-00rel0\logical\cmsdk_ahb_to_apb_async\verilog\cmsdk_ahb_to_apb_async_h.v 9740 2017-10-02
AT510-MN-80001-r2p0-00rel0\logical\cmsdk_ahb_to_apb_async\verilog\cmsdk_ahb_to_apb_async_p.v 7822 2017-10-02
AT510-MN-80001-r2p0-00rel0\logical\cmsdk_ahb_to_apb_async\verilog\cmsdk_ahb_to_apb_async_syn.v 2290 2017-10-02
AT510-MN-80001-r2p0-00rel0\logical\cmsdk_ahb_to_extmem16\verilog\cmsdk_ahb_to_extmem16.v 16944 2017-10-02
AT510-MN-80001-r2p0-00rel0\logical\cmsdk_ahb_to_extmem16\verilog\cmsdk_ahb_to_extmem16_ahb_fsm.v 22742 2017-10-02
AT510-MN-80001-r2p0-00rel0\logical\cmsdk_ahb_to_extmem16\verilog\cmsdk_ahb_to_extmem16_mem_fsm.v 16309 2017-10-02
AT510-MN-80001-r2p0-00rel0\logical\cmsdk_ahb_to_flash16\verilog\cmsdk_ahb_to_flash16.v 5598 2017-10-02
AT510-MN-80001-r2p0-00rel0\logical\cmsdk_ahb_to_flash32\verilog\cmsdk_ahb_to_flash32.v 5767 2017-10-02
AT510-MN-80001-r2p0-00rel0\logical\cmsdk_ahb_to_sram\verilog\cmsdk_ahb_to_sram.v 16146 2017-10-02
AT510-MN-80001-r2p0-00rel0\logical\cmsdk_ahb_upsizer64\verilog\cmsdk_ahb_upsizer64.v 3758 2017-10-02
AT510-MN-80001-r2p0-00rel0\logical\cmsdk_apb3_eg_slave\verilog\cmsdk_apb3_eg_slave.v 5157 2017-10-02
AT510-MN-80001-r2p0-00rel0\logical\cmsdk_apb3_eg_slave\verilog\cmsdk_apb3_eg_slave_interface.v 3831 2017-10-02
AT510-MN-80001-r2p0-00rel0\logical\cmsdk_apb3_eg_slave\verilog\cmsdk_apb3_eg_slave_reg.v 7743 2017-10-02
AT510-MN-80001-r2p0-00rel0\logical\cmsdk_apb4_eg_slave\verilog\cmsdk_apb4_eg_slave.v 5349 2017-10-02
AT510-MN-80001-r2p0-00rel0\logical\cmsdk_apb4_eg_slave\verilog\cmsdk_apb4_eg_slave_interface.v 3935 2017-10-02
AT510-MN-80001-r2p0-00rel0\logical\cmsdk_apb4_eg_slave\verilog\cmsdk_apb4_eg_slave_reg.v 8769 2017-10-02
AT510-MN-80001-r2p0-00rel0\logical\cmsdk_apb_dualtimers\verilog\cmsdk_apb_dualtimers.v 12711 2017-10-02
AT510-MN-80001-r2p0-00rel0\logical\cmsdk_apb_dualtimers\verilog\cmsdk_apb_dualtimers_defs.v 2731 2017-10-02
AT510-MN-80001-r2p0-00rel0\logical\cmsdk_apb_dualtimers\verilog\cmsdk_apb_dualtimers_frc.v 22660 2017-10-02
AT510-MN-80001-r2p0-00rel0\logical\cmsdk_apb_slave_mux\verilog\cmsdk_apb_slave_mux.v 8445 2017-10-02
AT510-MN-80001-r2p0-00rel0\logical\cmsdk_apb_subsystem\verilog\cmsdk_apb_subsystem.v 33820 2017-10-02
AT510-MN-80001-r2p0-00rel0\logical\cmsdk_apb_subsystem\verilog\cmsdk_apb_subsystem_m0ds.v 40287 2017-10-02
AT510-MN-80001-r2p0-00rel0\logical\cmsdk_apb_subsystem\verilog\cmsdk_apb_test_slave.v 5211 2017-10-02
AT510-MN-80001-r2p0-00rel0\logical\cmsdk_apb_subsystem\verilog\cmsdk_irq_sync.v 1593 2017-10-02
AT510-MN-80001-r2p0-00rel0\logical\cmsdk_apb_timeout_mon\verilog\cmsdk_apb_timeout_mon.v 15537 2017-10-02
AT510-MN-80001-r2p0-00rel0\logical\cmsdk_apb_timer\verilog\cmsdk_apb_timer.v 20785 2017-10-02
AT510-MN-80001-r2p0-00rel0\logical\cmsdk_apb_uart\verilog\cmsdk_apb_uart.v 42035 2017-10-02
AT510-MN-80001-r2p0-00rel0\logical\cmsdk_apb_watchdog\verilog\cmsdk_apb_watchdog.v 13003 2017-10-02
AT510-MN-80001-r2p0-00rel0\logical\cmsdk_apb_watchdog\verilog\cmsdk_apb_watchdog_defs.v 2556 2017-10-02
AT510-MN-80001-r2p0-00rel0\logical\cmsdk_apb_watchdog\verilog\cmsdk_apb_watchdog_frc.v 20026 2017-10-02
AT510-MN-80001-r2p0-00rel0\logical\cmsdk_debug_tester\verilog\cmsdk_debug_tester.v 44211 2017-10-02
AT510-MN-80001-r2p0-00rel0\logical\cmsdk_debug_tester\verilog\cmsdk_debug_tester_ahb_interconnect.v 5496 2017-10-02
AT510-MN-80001-r2p0-00rel0\logical\cmsdk_debug_tester\verilog\cmsdk_debug_tester_trace_capture.v 15894 2017-10-02
AT510-MN-80001-r2p0-00rel0\logical\cmsdk_fpga_sram\verilog\cmsdk_fpga_sram.v 3540 2017-10-02
AT510-MN-80001-r2p0-00rel0\logical\cmsdk_iop_gpio\verilog\cmsdk_iop_gpio.v 40609 2017-10-02
AT510-MN-80001-r2p0-00rel0\logical\cmsdk_mcu_mtx4x2\README.txt 1861 2017-10-02
AT510-MN-80001-r2p0-00rel0\logical\cmsdk_mcu_mtx4x2\verilog\cmsdk_mcu_mtx4x2.v 33219 2017-10-02
AT510-MN-80001-r2p0-00rel0\logical\cmsdk_mcu_mtx4x2\verilog\cmsdk_mcu_mtx4x2_arb_M0.v 6155 2017-10-02
AT510-MN-80001-r2p0-00rel0\logical\cmsdk_mcu_mtx4x2\verilog\cmsdk_mcu_mtx4x2_arb_M1.v 5853 2017-10-02
AT510-MN-80001-r2p0-00rel0\logical\cmsdk_mcu_mtx4x2\verilog\cmsdk_mcu_mtx4x2_dec_S0.v 11752 2017-10-02
AT510-MN-80001-r2p0-00rel0\logical\cmsdk_mcu_mtx4x2\verilog\cmsdk_mcu_mtx4x2_dec_S1.v 10203 2017-10-02
AT510-MN-80001-r2p0-00rel0\logical\cmsdk_mcu_mtx4x2\verilog\cmsdk_mcu_mtx4x2_dec_S2.v 10203 2017-10-02
AT510-MN-80001-r2p0-00rel0\logical\cmsdk_mcu_mtx4x2\verilog\cmsdk_mcu_mtx4x2_dec_S3.v 10203 2017-10-02

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