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文件名称:317010258lab30

  • 所属分类：
    其他
  • 标签属性：
    [VHDL] [源码]
  • 上传时间：
    2020-01-02
  • 文件大小：
    5.51mb
  • 已下载：
    1次
  • 提 供 者：
    败*****
  • 相关连接：
    无
  • 下载说明：
    别用迅雷下载，失败请重下，重下不扣分！
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介绍说明－－下载内容来自于网络，使用问题请自行百度

计算机组成lab30流水线，　　　。　。(pipeline,zju,abcdefg,using)
相关搜索： lab30

(系统自动生成,下载前可以参看下载内容)

下载文件列表

文件名大小更新时间
3170102584_王超群_lab30\3170102584_lab30.docx 1226671 2019-12-24
3170102584_王超群_lab30\sim\risc-v.cr.mti 3982 2019-12-24
3170102584_王超群_lab30\sim\risc-v.mpf 102472 2019-12-24
3170102584_王超群_lab30\sim\vsim.wlf 49152 2019-12-23
3170102584_王超群_lab30\sim\work\@_opt\_lib.qdb 49152 2019-12-23
3170102584_王超群_lab30\sim\work\@_opt\_lib1_0.qdb 32768 2019-12-23
3170102584_王超群_lab30\sim\work\@_opt\_lib1_0.qpg 0 2019-12-23
3170102584_王超群_lab30\sim\work\@_opt\_lib1_0.qtl 9325 2019-12-23
3170102584_王超群_lab30\sim\work\@_opt\_lib2_0.qdb 32768 2019-12-23
3170102584_王超群_lab30\sim\work\@_opt\_lib2_0.qpg 0 2019-12-23
3170102584_王超群_lab30\sim\work\@_opt\_lib2_0.qtl 7814 2019-12-23
3170102584_王超群_lab30\sim\work\@_opt\_lib3_0.qdb 32768 2019-12-23
3170102584_王超群_lab30\sim\work\@_opt\_lib3_0.qpg 0 2019-12-23
3170102584_王超群_lab30\sim\work\@_opt\_lib3_0.qtl 6466 2019-12-23
3170102584_王超群_lab30\sim\work\@_opt\_lib4_0.qdb 32768 2019-12-23
3170102584_王超群_lab30\sim\work\@_opt\_lib4_0.qpg 0 2019-12-23
3170102584_王超群_lab30\sim\work\@_opt\_lib4_0.qtl 4560 2019-12-23
3170102584_王超群_lab30\sim\work\_info 6019 2019-12-23
3170102584_王超群_lab30\sim\work\_lib.qdb 49152 2019-12-23
3170102584_王超群_lab30\sim\work\_lib1_0.qdb 32768 2019-12-23
3170102584_王超群_lab30\sim\work\_lib1_0.qpg 868352 2019-12-23
3170102584_王超群_lab30\sim\work\_lib1_0.qtl 292497 2019-12-23
3170102584_王超群_lab30\sim\work\_vmake 29 2019-12-23
3170102584_王超群_lab30\src\adder_32bits.v 1762 2019-09-11
3170102584_王超群_lab30\src\adder_4bits.v 791 2019-09-11
3170102584_王超群_lab30\src\ALU.v 1327 2019-12-23
3170102584_王超群_lab30\src\ALU.v.bak 1315 2019-12-22
3170102584_王超群_lab30\src\ALU_tb.v 1332 2019-10-10
3170102584_王超群_lab30\src\DataRAM.v 3596 2019-12-02
3170102584_王超群_lab30\src\Decode.v 6434 2019-12-23
3170102584_王超群_lab30\src\Decode.v.bak 6369 2019-12-23
3170102584_王超群_lab30\src\Decode_tb.v 1636 2019-10-08
3170102584_王超群_lab30\src\dff_lib.v 714 2019-11-16
3170102584_王超群_lab30\src\dist_mem_gen_v8_0.v 16441 2019-12-22
3170102584_王超群_lab30\src\EX.v 2301 2019-12-22
3170102584_王超群_lab30\src\EX.v.bak 2187 2019-12-03
3170102584_王超群_lab30\src\ID.v 4374 2019-12-23
3170102584_王超群_lab30\src\ID.v.bak 4364 2019-12-23
3170102584_王超群_lab30\src\IF.v 1168 2019-12-02
3170102584_王超群_lab30\src\IF_tb.v 1125 2019-10-08
3170102584_王超群_lab30\src\InstructionROM.v 1753 2019-09-29
3170102584_王超群_lab30\src\Registers.v 727 2019-12-23
3170102584_王超群_lab30\src\Registers.v.bak 709 2019-12-22
3170102584_王超群_lab30\src\Risc5CPU.v 5503 2019-12-23
3170102584_王超群_lab30\src\Risc5CPU.v.bak 5539 2019-12-03
3170102584_王超群_lab30\src\Risc5CPU_tb.v 815 2019-12-03
3170102584_王超群_lab30\vivado\Risc5CPU.cache\ip\2017.4\491ccdee2535ddf3\491ccdee2535ddf3.xci 6821 2019-12-23
3170102584_王超群_lab30\vivado\Risc5CPU.cache\ip\2017.4\491ccdee2535ddf3\DisplayROM.dcp 22049 2019-12-23
3170102584_王超群_lab30\vivado\Risc5CPU.cache\ip\2017.4\491ccdee2535ddf3\DisplayROM_sim_netlist.v 18262 2019-12-23
3170102584_王超群_lab30\vivado\Risc5CPU.cache\ip\2017.4\491ccdee2535ddf3\DisplayROM_sim_netlist.vhdl 26998 2019-12-23
3170102584_王超群_lab30\vivado\Risc5CPU.cache\ip\2017.4\491ccdee2535ddf3\DisplayROM_stub.v 1316 2019-12-23
3170102584_王超群_lab30\vivado\Risc5CPU.cache\ip\2017.4\491ccdee2535ddf3\DisplayROM_stub.vhdl 1457 2019-12-23
3170102584_王超群_lab30\vivado\Risc5CPU.cache\ip\2017.4\491ccdee2535ddf3.logs\runme.log 28476 2019-12-23
3170102584_王超群_lab30\vivado\Risc5CPU.cache\ip\2017.4\79da96088df10aa0\79da96088df10aa0.xci 6829 2019-12-23
3170102584_王超群_lab30\vivado\Risc5CPU.cache\ip\2017.4\79da96088df10aa0\DataRAM.dcp 32557 2019-12-23
3170102584_王超群_lab30\vivado\Risc5CPU.cache\ip\2017.4\79da96088df10aa0\DataRAM_sim_netlist.v 25101 2019-12-23
3170102584_王超群_lab30\vivado\Risc5CPU.cache\ip\2017.4\79da96088df10aa0\DataRAM_sim_netlist.vhdl 36377 2019-12-23
3170102584_王超群_lab30\vivado\Risc5CPU.cache\ip\2017.4\79da96088df10aa0\DataRAM_stub.v 1358 2019-12-23
3170102584_王超群_lab30\vivado\Risc5CPU.cache\ip\2017.4\79da96088df10aa0\DataRAM_stub.vhdl 1532 2019-12-23
3170102584_王超群_lab30\vivado\Risc5CPU.cache\ip\2017.4\79da96088df10aa0.logs\runme.log 29190 2019-12-23
3170102584_王超群_lab30\vivado\Risc5CPU.cache\wt\gui_handlers.wdf 2692 2019-12-24
3170102584_王超群_lab30\vivado\Risc5CPU.cache\wt\gui_resources.wdf 3086 2019-10-08
3170102584_王超群_lab30\vivado\Risc5CPU.cache\wt\java_command_handlers.wdf 1493 2019-12-24
3170102584_王超群_lab30\vivado\Risc5CPU.cache\wt\project.wpc 121 2019-12-24
3170102584_王超群_lab30\vivado\Risc5CPU.cache\wt\synthesis.wdf 5406 2019-12-23
3170102584_王超群_lab30\vivado\Risc5CPU.cache\wt\synthesis_details.wdf 100 2019-12-23
3170102584_王超群_lab30\vivado\Risc5CPU.cache\wt\webtalk_pa.xml 3761 2019-12-24
3170102584_王超群_lab30\vivado\Risc5CPU.hw\hw_1\hw.xml 844 2019-12-24
3170102584_王超群_lab30\vivado\Risc5CPU.hw\Risc5CPU.lpr 343 2019-12-24
3170102584_王超群_lab30\vivado\Risc5CPU.ip_user_files\ip\DataRAM\DataRAM.veo 3019 2019-12-23
3170102584_王超群_lab30\vivado\Risc5CPU.ip_user_files\ip\DataRAM\DataRAM.vho 3275 2019-12-23
3170102584_王超群_lab30\vivado\Risc5CPU.ip_user_files\ip\DataRAM\DataRAM_stub.v 1251 2019-12-23
3170102584_王超群_lab30\vivado\Risc5CPU.ip_user_files\ip\DataRAM\DataRAM_stub.vhdl 1357 2019-12-23
3170102584_王超群_lab30\vivado\Risc5CPU.ip_user_files\ip\DCM_PLL\DCM_PLL.veo 3756 2019-10-08
3170102584_王超群_lab30\vivado\Risc5CPU.ip_user_files\ip\DCM_PLL\DCM_PLL_stub.v 1257 2019-10-08
3170102584_王超群_lab30\vivado\Risc5CPU.ip_user_files\ip\DCM_PLL\DCM_PLL_stub.vhdl 1226 2019-10-08
3170102584_王超群_lab30\vivado\Risc5CPU.ip_user_files\ip\DisplayROM\DisplayROM.veo 2964 2019-10-08
3170102584_王超群_lab30\vivado\Risc5CPU.ip_user_files\ip\DisplayROM\DisplayROM.vho 3198 2019-10-08
3170102584_王超群_lab30\vivado\Risc5CPU.ip_user_files\ip\DisplayROM\DisplayROM_stub.v 1233 2019-12-23
3170102584_王超群_lab30\vivado\Risc5CPU.ip_user_files\ip\DisplayROM\DisplayROM_stub.vhdl 1312 2019-12-23
3170102584_王超群_lab30\vivado\Risc5CPU.ip_user_files\ipstatic\simulation\dist_mem_gen_v8_0.v 16441 2019-10-08
3170102584_王超群_lab30\vivado\Risc5CPU.ip_user_files\mem_init_files\digital.coe 2881 2019-10-08
3170102584_王超群_lab30\vivado\Risc5CPU.ip_user_files\mem_init_files\DisplayROM.mif 2304 2019-10-08
3170102584_王超群_lab30\vivado\Risc5CPU.ip_user_files\README.txt 130 2019-10-08
3170102584_王超群_lab30\vivado\Risc5CPU.ip_user_files\sim_scripts\DataRAM\activehdl\compile.do 677 2019-12-23
3170102584_王超群_lab30\vivado\Risc5CPU.ip_user_files\sim_scripts\DataRAM\activehdl\DataRAM.sh 4816 2019-12-23
3170102584_王超群_lab30\vivado\Risc5CPU.ip_user_files\sim_scripts\DataRAM\activehdl\DataRAM.udo 0 2019-12-23
3170102584_王超群_lab30\vivado\Risc5CPU.ip_user_files\sim_scripts\DataRAM\activehdl\file_info.txt 410 2019-12-23
3170102584_王超群_lab30\vivado\Risc5CPU.ip_user_files\sim_scripts\DataRAM\activehdl\glbl.v 1474 2017-12-14
3170102584_王超群_lab30\vivado\Risc5CPU.ip_user_files\sim_scripts\DataRAM\activehdl\README.txt 2171 2019-12-23
3170102584_王超群_lab30\vivado\Risc5CPU.ip_user_files\sim_scripts\DataRAM\activehdl\simulate.do 324 2019-12-23
3170102584_王超群_lab30\vivado\Risc5CPU.ip_user_files\sim_scripts\DataRAM\activehdl\wave.do 32 2019-12-23
3170102584_王超群_lab30\vivado\Risc5CPU.ip_user_files\sim_scripts\DataRAM\ies\DataRAM.sh 5631 2019-12-23
3170102584_王超群_lab30\vivado\Risc5CPU.ip_user_files\sim_scripts\DataRAM\ies\file_info.txt 410 2019-12-23
3170102584_王超群_lab30\vivado\Risc5CPU.ip_user_files\sim_scripts\DataRAM\ies\glbl.v 1474 2017-12-14
3170102584_王超群_lab30\vivado\Risc5CPU.ip_user_files\sim_scripts\DataRAM\ies\README.txt 2112 2019-12-23
3170102584_王超群_lab30\vivado\Risc5CPU.ip_user_files\sim_scripts\DataRAM\ies\run.f 478 2019-12-23
3170102584_王超群_lab30\vivado\Risc5CPU.ip_user_files\sim_scripts\DataRAM\modelsim\compile.do 761 2019-12-23
3170102584_王超群_lab30\vivado\Risc5CPU.ip_user_files\sim_scripts\DataRAM\modelsim\DataRAM.sh 5029 2019-12-23
3170102584_王超群_lab30\vivado\Risc5CPU.ip_user_files\sim_scripts\DataRAM\modelsim\DataRAM.udo 0 2019-12-23

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