CDN加速镜像 | 设为首页 | 加入收藏夹
登陆 | 会员注册
当前位置： 首页 资源下载 源码下载 嵌入式/单片机编程 VHDL编程
收藏

文件名称:verilog-axi-master

  • 所属分类：
    VHDL/FPGA/Verilog
  • 标签属性：
    [VHDL] [源码]
  • 上传时间：
    2020-04-23
  • 文件大小：
    306kb
  • 已下载：
    4次
  • 提 供 者：
    viyef*****
  • 相关连接：
    无
  • 下载说明：
    别用迅雷下载，失败请重下，重下不扣分！
修正介绍说明

介绍说明－－下载内容来自于网络，使用问题请自行百度

Verilog AXI Components Readme

GitHub repository: alexforencich verilog-axi
相关搜索： AXI verilog

(系统自动生成,下载前可以参看下载内容)

下载文件列表

文件名大小更新时间
verilog-axi-master 0 2020-04-13
verilog-axi-master\.gitignore 33 2020-04-13
verilog-axi-master\AUTHORS 40 2020-04-13
verilog-axi-master\COPYING 1057 2020-04-13
verilog-axi-master\README 9 2020-04-13
verilog-axi-master\README.md 16211 2020-04-13
verilog-axi-master\rtl 0 2020-04-13
verilog-axi-master\rtl\arbiter.v 4892 2020-04-13
verilog-axi-master\rtl\axi_adapter.v 11358 2020-04-13
verilog-axi-master\rtl\axi_adapter_rd.v 29139 2020-04-13
verilog-axi-master\rtl\axi_adapter_wr.v 33550 2020-04-13
verilog-axi-master\rtl\axi_axil_adapter.v 7882 2020-04-13
verilog-axi-master\rtl\axi_axil_adapter_rd.v 21729 2020-04-13
verilog-axi-master\rtl\axi_axil_adapter_wr.v 24215 2020-04-13
verilog-axi-master\rtl\axi_cdma.v 30817 2020-04-13
verilog-axi-master\rtl\axi_cdma_desc_mux.v 9965 2020-04-13
verilog-axi-master\rtl\axi_crossbar.v 14981 2020-04-13
verilog-axi-master\rtl\axi_crossbar_addr.v 14356 2020-04-13
verilog-axi-master\rtl\axi_crossbar_rd.v 23589 2020-04-13
verilog-axi-master\rtl\axi_crossbar_wr.v 28129 2020-04-13
verilog-axi-master\rtl\axi_dma.v 12759 2020-04-13
verilog-axi-master\rtl\axi_dma_desc_mux.v 13235 2020-04-13
verilog-axi-master\rtl\axi_dma_rd.v 28976 2020-04-13
verilog-axi-master\rtl\axi_dma_wr.v 39583 2020-04-13
verilog-axi-master\rtl\axi_dp_ram.v 14505 2020-04-13
verilog-axi-master\rtl\axi_fifo.v 10829 2020-04-13
verilog-axi-master\rtl\axi_fifo_rd.v 13965 2020-04-13
verilog-axi-master\rtl\axi_fifo_wr.v 15278 2020-04-13
verilog-axi-master\rtl\axi_interconnect.v 41736 2020-04-13
verilog-axi-master\rtl\axi_ram.v 13310 2020-04-13
verilog-axi-master\rtl\axi_ram_rd_if.v 10000 2020-04-13
verilog-axi-master\rtl\axi_ram_wr_if.v 10507 2020-04-13
verilog-axi-master\rtl\axi_ram_wr_rd_if.v 11874 2020-04-13
verilog-axi-master\rtl\axi_register.v 11108 2020-04-13
verilog-axi-master\rtl\axi_register_rd.v 18862 2020-04-13
verilog-axi-master\rtl\axi_register_wr.v 24026 2020-04-13
verilog-axi-master\rtl\axil_adapter.v 5793 2020-04-13
verilog-axi-master\rtl\axil_adapter_rd.v 10081 2020-04-13
verilog-axi-master\rtl\axil_adapter_wr.v 12684 2020-04-13
verilog-axi-master\rtl\axil_cdc.v 5465 2020-04-13
verilog-axi-master\rtl\axil_cdc_rd.v 6352 2020-04-13
verilog-axi-master\rtl\axil_cdc_wr.v 7454 2020-04-13
verilog-axi-master\rtl\axil_dp_ram.v 11480 2020-04-13
verilog-axi-master\rtl\axil_interconnect.v 21865 2020-04-13
verilog-axi-master\rtl\axil_ram.v 6183 2020-04-13
verilog-axi-master\rtl\axil_register.v 6033 2020-04-13
verilog-axi-master\rtl\axil_register_rd.v 11758 2020-04-13
verilog-axi-master\rtl\axil_register_wr.v 16194 2020-04-13
verilog-axi-master\rtl\priority_encoder.v 3205 2020-04-13
verilog-axi-master\syn 0 2020-04-13
verilog-axi-master\syn\axil_cdc.tcl 4109 2020-04-13
verilog-axi-master\tb 0 2020-04-13
verilog-axi-master\tb\axi.py 35529 2020-04-13
verilog-axi-master\tb\axil.py 19674 2020-04-13
verilog-axi-master\tb\axis_ep.py 18128 2020-04-13
verilog-axi-master\tb\test_axi.py 11390 2020-04-13
verilog-axi-master\tb\test_axi_adapter_16_32.py 16522 2020-04-13
verilog-axi-master\tb\test_axi_adapter_16_32.v 10000 2020-04-13
verilog-axi-master\tb\test_axi_adapter_32_16.py 16548 2020-04-13
verilog-axi-master\tb\test_axi_adapter_32_16.v 10000 2020-04-13
verilog-axi-master\tb\test_axi_adapter_32_32.py 16548 2020-04-13
verilog-axi-master\tb\test_axi_adapter_32_32.v 10000 2020-04-13
verilog-axi-master\tb\test_axi_axil_adapter_16_32.py 13632 2020-04-13
verilog-axi-master\tb\test_axi_axil_adapter_16_32.v 6673 2020-04-13
verilog-axi-master\tb\test_axi_axil_adapter_32_16.py 13608 2020-04-13
verilog-axi-master\tb\test_axi_axil_adapter_32_16.v 6673 2020-04-13
verilog-axi-master\tb\test_axi_axil_adapter_32_32.py 13208 2020-04-13
verilog-axi-master\tb\test_axi_axil_adapter_32_32.v 6673 2020-04-13
verilog-axi-master\tb\test_axi_cdma_32.py 11242 2020-04-13
verilog-axi-master\tb\test_axi_cdma_32.v 5904 2020-04-13
verilog-axi-master\tb\test_axi_cdma_32_unaligned.py 11244 2020-04-13
verilog-axi-master\tb\test_axi_cdma_32_unaligned.v 5934 2020-04-13
verilog-axi-master\tb\test_axi_crossbar_4x4.py 31798 2020-04-13
verilog-axi-master\tb\test_axi_crossbar_4x4.v 12019 2020-04-13
verilog-axi-master\tb\test_axi_dma_32_32.py 19466 2020-04-13
verilog-axi-master\tb\test_axi_dma_32_32.v 10926 2020-04-13
verilog-axi-master\tb\test_axi_dma_rd_32_32.py 11276 2020-04-13
verilog-axi-master\tb\test_axi_dma_rd_32_32.v 6593 2020-04-13
verilog-axi-master\tb\test_axi_dma_rd_32_32_unaligned.py 11282 2020-04-13
verilog-axi-master\tb\test_axi_dma_rd_32_32_unaligned.v 6623 2020-04-13
verilog-axi-master\tb\test_axi_dma_wr_32_32.py 12517 2020-04-13
verilog-axi-master\tb\test_axi_dma_wr_32_32.v 7182 2020-04-13
verilog-axi-master\tb\test_axi_dma_wr_32_32_unaligned.py 12523 2020-04-13
verilog-axi-master\tb\test_axi_dma_wr_32_32_unaligned.v 7212 2020-04-13
verilog-axi-master\tb\test_axi_dp_ram.py 18204 2020-04-13
verilog-axi-master\tb\test_axi_dp_ram.v 8458 2020-04-13
verilog-axi-master\tb\test_axi_fifo.py 16089 2020-04-13
verilog-axi-master\tb\test_axi_fifo.v 9887 2020-04-13
verilog-axi-master\tb\test_axi_fifo_delay.py 16095 2020-04-13
verilog-axi-master\tb\test_axi_fifo_delay.v 9905 2020-04-13
verilog-axi-master\tb\test_axi_interconnect_4x4.py 29947 2020-04-13
verilog-axi-master\tb\test_axi_interconnect_4x4.v 11037 2020-04-13
verilog-axi-master\tb\test_axi_ram.py 9380 2020-04-13
verilog-axi-master\tb\test_axi_ram.v 4678 2020-04-13
verilog-axi-master\tb\test_axi_register.py 16098 2020-04-13
verilog-axi-master\tb\test_axi_register.v 9900 2020-04-13
verilog-axi-master\tb\test_axil.py 8989 2020-04-13
verilog-axi-master\tb\test_axil_adapter_16_32.py 10940 2020-04-13
verilog-axi-master\tb\test_axil_adapter_16_32.v 5162 2020-04-13
verilog-axi-master\tb\test_axil_adapter_32_16.py 10940 2020-04-13

相关说明

  • 本站资源为会员上传分享交流与学习,如有侵犯您的权益,请联系我们删除.
  • 搜珍网是交换下载平台，只提供交流渠道，下载内容来自于网络，除下载问题外，其它问题请自行百度。更多...
  • 本站已设置防盗链，请勿用迅雷、QQ旋风等下载软件下载资源，下载后用WinRAR最新版进行解压.
  • 如果您发现内容无法下载，请稍后再次尝试；或换浏览器；或者到消费记录里找到下载记录反馈给我们.
  • 下载后发现下载的内容跟说明不相乎，请到消费记录里找到下载记录反馈给我们，经确认后退回积分.
  • 如下载前有疑问，可以通过点击"提供者"的名字，查看对方的联系方式，联系对方咨询.
查看所有评论

相关评论

暂无评论内容．

发表评论

*快速评论： 推荐 一般 有密码 和说明不符 不是源码或资料 文件不全 不能解压 纯粹是垃圾
*内　　容：
*验 证 码：
搜珍网 www.dssz.com