压缩包 : verilog.rar 列表
verilog/atan_lut.coe
verilog/atan_lut.mif
verilog/bits_to_bytes.v
verilog/calc_mean.v
verilog/common_defs.v
verilog/common_params.v
verilog/complex_mult.v
verilog/complex_to_mag.v
verilog/complex_to_mag_sq.v
verilog/coregen/atan_lut.asy
verilog/coregen/atan_lut.gise
verilog/coregen/atan_lut.mif
verilog/coregen/atan_lut.ncf
verilog/coregen/atan_lut.ngc
verilog/coregen/atan_lut.sym
verilog/coregen/atan_lut.v
verilog/coregen/atan_lut.veo
verilog/coregen/atan_lut.vhd
verilog/coregen/atan_lut.vho
verilog/coregen/atan_lut.xco
verilog/coregen/atan_lut.xise
verilog/coregen/atan_lut_flist.txt
verilog/coregen/atan_lut_xmdf.tcl
verilog/coregen/complex_multiplier.asy
verilog/coregen/complex_multiplier.gise
verilog/coregen/complex_multiplier.ncf
verilog/coregen/complex_multiplier.ngc
verilog/coregen/complex_multiplier.sym
verilog/coregen/complex_multiplier.v
verilog/coregen/complex_multiplier.veo
verilog/coregen/complex_multiplier.vhd
verilog/coregen/complex_multiplier.vho
verilog/coregen/complex_multiplier.xco
verilog/coregen/complex_multiplier.xise
verilog/coregen/complex_multiplier_flist.txt
verilog/coregen/complex_multiplier_readme.txt
verilog/coregen/complex_multiplier_xmdf.tcl
verilog/coregen/deinter_lut.asy
verilog/coregen/deinter_lut.gise
verilog/coregen/deinter_lut.mif
verilog/coregen/deinter_lut.ncf
verilog/coregen/deinter_lut.ngc
verilog/coregen/deinter_lut.sym
verilog/coregen/deinter_lut.v
verilog/coregen/deinter_lut.veo
verilog/coregen/deinter_lut.vhd
verilog/coregen/deinter_lut.vho
verilog/coregen/deinter_lut.xco
verilog/coregen/deinter_lut.xise
verilog/coregen/deinter_lut_flist.txt
verilog/coregen/deinter_lut_xmdf.tcl
verilog/coregen/div_gen_new_ip_core_zynq/component.xml
verilog/coregen/div_gen_new_ip_core_zynq/src/div_gen.v
verilog/coregen/div_gen_new_ip_core_zynq/src/div_gen_div_gen_0_0/div_gen_div_gen_0_0.xci
verilog/coregen/div_gen_new_ip_core_zynq/src/div_gen_ooc.xdc
verilog/coregen/div_gen_new_ip_core_zynq/src/div_gen_xlslice_0_0/div_gen_xlslice_0_0.xci
verilog/coregen/div_gen_new_ip_core_zynquplus/component.xml
verilog/coregen/div_gen_new_ip_core_zynquplus/src/div_gen.v
verilog/coregen/div_gen_new_ip_core_zynquplus/src/div_gen_div_gen_0_0/div_gen_div_gen_0_0.xci
verilog/coregen/div_gen_new_ip_core_zynquplus/src/div_gen_ooc.xdc
verilog/coregen/div_gen_new_ip_core_zynquplus/src/div_gen_xlslice_0_0/div_gen_xlslice_0_0.xci
verilog/coregen/div_gen_new_src/div_gen.bd
verilog/coregen/div_gen_v3_0.asy
verilog/coregen/div_gen_v3_0.gise
verilog/coregen/div_gen_v3_0.ncf
verilog/coregen/div_gen_v3_0.ngc
verilog/coregen/div_gen_v3_0.sym
verilog/coregen/div_gen_v3_0.v
verilog/coregen/div_gen_v3_0.veo
verilog/coregen/div_gen_v3_0.vhd
verilog/coregen/div_gen_v3_0.vho
verilog/coregen/div_gen_v3_0.xco
verilog/coregen/div_gen_v3_0.xise
verilog/coregen/div_gen_v3_0_flist.txt
verilog/coregen/div_gen_v3_0_readme.txt
verilog/coregen/div_gen_v3_0_xmdf.tcl
verilog/coregen/rot_lut.asy
verilog/coregen/rot_lut.gise
verilog/coregen/rot_lut.mif
verilog/coregen/rot_lut.ncf
verilog/coregen/rot_lut.ngc
verilog/coregen/rot_lut.sym
verilog/coregen/rot_lut.v
verilog/coregen/rot_lut.veo
verilog/coregen/rot_lut.vhd
verilog/coregen/rot_lut.vho
verilog/coregen/rot_lut.xco
verilog/coregen/rot_lut.xise
verilog/coregen/viterbi_v7_0.asy
verilog/coregen/viterbi_v7_0.gise
verilog/coregen/viterbi_v7_0.ncf
verilog/coregen/viterbi_v7_0.ngc
verilog/coregen/viterbi_v7_0.sym
verilog/coregen/viterbi_v7_0.v
verilog/coregen/viterbi_v7_0.veo
verilog/coregen/viterbi_v7_0.vhd
verilog/coregen/viterbi_v7_0.vho
verilog/coregen/viterbi_v7_0.xco
verilog/coregen/viterbi_v7_0.xise
verilog/coregen/viterbi_v7_0rombram.mif
verilog/coregen/viterbi_v7_0romlifo.mif
verilog/coregen/viterbi_v7_0romwe.mif
verilog/coregen/viterbi_v7_0_flist.txt
verilog/coregen/viterbi_v7_0_readme.txt
verilog/coregen/viterbi_v7_0_xmdf.tcl
verilog/coregen/xfft_v7_1.asy
verilog/coregen/xfft_v7_1.gise
verilog/coregen/xfft_v7_1.ncf
verilog/coregen/xfft_v7_1.ngc
verilog/coregen/xfft_v7_1.sym
verilog/coregen/xfft_v7_1.v
verilog/coregen/xfft_v7_1.veo
verilog/coregen/xfft_v7_1.vhd
verilog/coregen/xfft_v7_1.vho
verilog/coregen/xfft_v7_1.xco
verilog/coregen/xfft_v7_1.xise
verilog/coregen/xfft_v7_1_flist.txt
verilog/coregen/xfft_v7_1_readme.txt
verilog/coregen/xfft_v7_1_xmdf.tcl
verilog/crc32.v
verilog/deinterleave.v
verilog/deinter_lut.coe
verilog/deinter_lut.mif
verilog/delayT.v
verilog/delay_sample.v
verilog/demodulate.v
verilog/descramble.v
verilog/divider.v
verilog/dot11.v
verilog/dot11_modules.list
verilog/dot11_side_ch_tb.v
verilog/dot11_tb.v
verilog/equalizer.v
verilog/ht_sig_crc.v
verilog/intf_64bit.v
verilog/last_sym_indicator.v
verilog/Makefile
verilog/moving_avg.v
verilog/ofdm_decoder.v
verilog/openofdm_rx.v
verilog/openofdm_rx_s_axi.v
verilog/phase.v
verilog/power_trigger.v
verilog/rand_gen.v
verilog/rand_gen_tb.v
verilog/rate_to_idx.v
verilog/rotate.v
verilog/rot_lut.coe
verilog/rot_lut.mif
verilog/sim_out/.gitignore
verilog/stage_mult.v
verilog/sync_long.v
verilog/sync_short.v
verilog/usrp2/ram_2port.v
verilog/usrp2/setting_reg.v
verilog/viterbi.v
verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/AFIF