文件名称:FPGA等精度频率计
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- 上传时间:2022-04-14
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文件大小:7.02mb
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先预置一个闸门信号,将该闸门信号作为D触发器的输入端,将被测信号作为D触发器的时钟,当闸门信号有效的时候(即从0到1的时候),在被测信号的上升沿来临的时候,闸门信号被送到D触发器的Q端口。D触发器的Q端口分别连接两个计数器,一个计数器对基准时钟计数(板子上的50M时钟或者用锁相环倍频后的高速时钟),另一个计数器对被测信号计数。当闸门信号有效被送到Q端口的时候,使能这两个计数器进行计数,当基准时钟计数到1s的时候,闸门信号拉低,无效(产生时间宽度为1s的闸门),计算这1s的时间内,被测信号计数了多少次,也就是被测信号经过了多少个时钟周期。
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压缩包 : 基于Basys3的等精度频率计.rar 列表 频率计/project_5/project_5.cache/wt/gui_resources.wdf 频率计/project_5/project_5.cache/wt/java_command_handlers.wdf 频率计/project_5/project_5.cache/wt/project.wpc 频率计/project_5/project_5.cache/wt/synthesis.wdf 频率计/project_5/project_5.cache/wt/synthesis_details.wdf 频率计/project_5/project_5.cache/wt/webtalk_pa.xml 频率计/project_5/project_5.cache/wt/xsim.wdf 频率计/project_5/project_5.hw/hw_1/hw.xml 频率计/project_5/project_5.hw/project_5.lpr 频率计/project_5/project_5.ip_user_files/README.txt 频率计/project_5/project_5.runs/.jobs/vrs_config_1.xml 频率计/project_5/project_5.runs/.jobs/vrs_config_2.xml 频率计/project_5/project_5.runs/impl_1/.init_design.begin.rst 频率计/project_5/project_5.runs/impl_1/.init_design.end.rst 频率计/project_5/project_5.runs/impl_1/.opt_design.begin.rst 频率计/project_5/project_5.runs/impl_1/.opt_design.end.rst 频率计/project_5/project_5.runs/impl_1/.place_design.begin.rst 频率计/project_5/project_5.runs/impl_1/.place_design.end.rst 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频率计/project_5/project_5.runs/impl_1/runme.sh 频率计/project_5/project_5.runs/impl_1/usage_statistics_webtalk.html 频率计/project_5/project_5.runs/impl_1/usage_statistics_webtalk.xml 频率计/project_5/project_5.runs/impl_1/vivado.jou 频率计/project_5/project_5.runs/impl_1/vivado.pb 频率计/project_5/project_5.runs/impl_1/write_bitstream.pb 频率计/project_5/project_5.runs/synth_1/.vivado.begin.rst 频率计/project_5/project_5.runs/synth_1/.vivado.end.rst 频率计/project_5/project_5.runs/synth_1/.Vivado_Synthesis.queue.rst 频率计/project_5/project_5.runs/synth_1/.Xil/frequency_counter_lcd1602_propImpl.xdc 频率计/project_5/project_5.runs/synth_1/frequency_counter_lcd1602.dcp 频率计/project_5/project_5.runs/synth_1/frequency_counter_lcd1602.tcl 频率计/project_5/project_5.runs/synth_1/frequency_counter_lcd1602.vds 频率计/project_5/project_5.runs/synth_1/frequency_counter_lcd1602_utilization_synth.pb 频率计/project_5/project_5.runs/synth_1/frequency_counter_lcd1602_utilization_synth.rpt 频率计/project_5/project_5.runs/synth_1/fsm_encoding.os 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