文件名称:dds_using_FPGA
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verilog编写基于fpga的DDS实现
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下载文件列表
dds_using_FPGA/cos.mif
dds_using_FPGA/cos_rom.bsf
dds_using_FPGA/cos_rom.inc
dds_using_FPGA/cos_rom.tdf
dds_using_FPGA/dds.asm.rpt
dds_using_FPGA/dds.done
dds_using_FPGA/dds.fit.rpt
dds_using_FPGA/dds.fit.smsg
dds_using_FPGA/dds.fit.summary
dds_using_FPGA/dds.flow.rpt
dds_using_FPGA/dds.map.rpt
dds_using_FPGA/dds.map.summary
dds_using_FPGA/dds.pin
dds_using_FPGA/dds.qpf
dds_using_FPGA/dds.qsf
dds_using_FPGA/dds.qws
dds_using_FPGA/dds.tan.rpt
dds_using_FPGA/dds.tan.summary
dds_using_FPGA/dds_lut.bdf
dds_using_FPGA/dds_lut.bsf
dds_using_FPGA/dds_lut.v
dds_using_FPGA/mux4.bsf
dds_using_FPGA/mux4.inc
dds_using_FPGA/mux4.tdf
dds_using_FPGA/ram.bsf
dds_using_FPGA/ram.inc
dds_using_FPGA/ram.tdf
dds_using_FPGA/sin.mif
dds_using_FPGA/sin_rom.bsf
dds_using_FPGA/sin_rom.inc
dds_using_FPGA/sin_rom.tdf
dds_using_FPGA/square.bsf
dds_using_FPGA/square.inc
dds_using_FPGA/square.tdf
dds_using_FPGA/squra.mif
dds_using_FPGA/db/add_sub_6fg.tdf
dds_using_FPGA/db/altsyncram_3u41.tdf
dds_using_FPGA/db/altsyncram_4pi2.tdf
dds_using_FPGA/db/altsyncram_90m1.tdf
dds_using_FPGA/db/altsyncram_9pi2.tdf
dds_using_FPGA/db/altsyncram_b431.tdf
dds_using_FPGA/db/altsyncram_ut41.tdf
dds_using_FPGA/db/altsyncram_vpl1.tdf
dds_using_FPGA/db/dds.(0).cnf.cdb
dds_using_FPGA/db/dds.(0).cnf.hdb
dds_using_FPGA/db/dds.(1).cnf.cdb
dds_using_FPGA/db/dds.(1).cnf.hdb
dds_using_FPGA/db/dds.(10).cnf.cdb
dds_using_FPGA/db/dds.(10).cnf.hdb
dds_using_FPGA/db/dds.(11).cnf.cdb
dds_using_FPGA/db/dds.(11).cnf.hdb
dds_using_FPGA/db/dds.(12).cnf.cdb
dds_using_FPGA/db/dds.(12).cnf.hdb
dds_using_FPGA/db/dds.(13).cnf.cdb
dds_using_FPGA/db/dds.(13).cnf.hdb
dds_using_FPGA/db/dds.(14).cnf.cdb
dds_using_FPGA/db/dds.(14).cnf.hdb
dds_using_FPGA/db/dds.(15).cnf.cdb
dds_using_FPGA/db/dds.(15).cnf.hdb
dds_using_FPGA/db/dds.(16).cnf.cdb
dds_using_FPGA/db/dds.(16).cnf.hdb
dds_using_FPGA/db/dds.(17).cnf.cdb
dds_using_FPGA/db/dds.(17).cnf.hdb
dds_using_FPGA/db/dds.(18).cnf.cdb
dds_using_FPGA/db/dds.(18).cnf.hdb
dds_using_FPGA/db/dds.(19).cnf.cdb
dds_using_FPGA/db/dds.(19).cnf.hdb
dds_using_FPGA/db/dds.(2).cnf.cdb
dds_using_FPGA/db/dds.(2).cnf.hdb
dds_using_FPGA/db/dds.(20).cnf.cdb
dds_using_FPGA/db/dds.(20).cnf.hdb
dds_using_FPGA/db/dds.(21).cnf.cdb
dds_using_FPGA/db/dds.(21).cnf.hdb
dds_using_FPGA/db/dds.(22).cnf.cdb
dds_using_FPGA/db/dds.(22).cnf.hdb
dds_using_FPGA/db/dds.(23).cnf.cdb
dds_using_FPGA/db/dds.(23).cnf.hdb
dds_using_FPGA/db/dds.(24).cnf.cdb
dds_using_FPGA/db/dds.(24).cnf.hdb
dds_using_FPGA/db/dds.(25).cnf.cdb
dds_using_FPGA/db/dds.(25).cnf.hdb
dds_using_FPGA/db/dds.(26).cnf.cdb
dds_using_FPGA/db/dds.(26).cnf.hdb
dds_using_FPGA/db/dds.(27).cnf.cdb
dds_using_FPGA/db/dds.(27).cnf.hdb
dds_using_FPGA/db/dds.(28).cnf.cdb
dds_using_FPGA/db/dds.(28).cnf.hdb
dds_using_FPGA/db/dds.(29).cnf.cdb
dds_using_FPGA/db/dds.(29).cnf.hdb
dds_using_FPGA/db/dds.(3).cnf.cdb
dds_using_FPGA/db/dds.(3).cnf.hdb
dds_using_FPGA/db/dds.(30).cnf.cdb
dds_using_FPGA/db/dds.(30).cnf.hdb
dds_using_FPGA/db/dds.(31).cnf.cdb
dds_using_FPGA/db/dds.(31).cnf.hdb
dds_using_FPGA/db/dds.(32).cnf.cdb
dds_using_FPGA/db/dds.(32).cnf.hdb
dds_using_FPGA/db/dds.(33).cnf.cdb
dds_using_FPGA/db/dds.(33).cnf.hdb
dds_using_FPGA/db/dds.(34).cnf.cdb
dds_using_FPGA/db/dds.(34).cnf.hdb
dds_using_FPGA/db/dds.(35).cnf.cdb
dds_using_FPGA/db/dds.(35).cnf.hdb
dds_using_FPGA/db/dds.(36).cnf.cdb
dds_using_FPGA/db/dds.(36).cnf.hdb
dds_using_FPGA/db/dds.(37).cnf.cdb
dds_using_FPGA/db/dds.(37).cnf.hdb
dds_using_FPGA/db/dds.(38).cnf.cdb
dds_using_FPGA/db/dds.(38).cnf.hdb
dds_using_FPGA/db/dds.(39).cnf.cdb
dds_using_FPGA/db/dds.(39).cnf.hdb
dds_using_FPGA/db/dds.(4).cnf.cdb
dds_using_FPGA/db/dds.(4).cnf.hdb
dds_using_FPGA/db/dds.(40).cnf.cdb
dds_using_FPGA/db/dds.(40).cnf.hdb
dds_using_FPGA/db/dds.(41).cnf.cdb
dds_using_FPGA/db/dds.(41).cnf.hdb
dds_using_FPGA/db/dds.(42).cnf.cdb
dds_using_FPGA/db/dds.(42).cnf.hdb
dds_using_FPGA/db/dds.(43).cnf.cdb
dds_using_FPGA/db/dds.(43).cnf.hdb
dds_using_FPGA/db/dds.(44).cnf.cdb
dds_using_FPGA/db/dds.(44).cnf.hdb
dds_using_FPGA/db/dds.(5).cnf.cdb
dds_using_FPGA/db/dds.(5).cnf.hdb
dds_using_FPGA/db/dds.(6).cnf.cdb
dds_using_FPGA/db/dds.(6).cnf.hdb
dds_using_FPGA/db/dds.(7).cnf.cdb
dds_using_FPGA/db/dds.(7).cnf.hdb
dds_using_FPGA/db/dds.(8).cnf.cdb
dds_using_FPGA/db/dds.(8).cnf.hdb
dds_using_FPGA/db/dds.(9).cnf.cdb
dds_using_FPGA/db/dds.(9).cnf.hdb
dds_using_FPGA/db/dds.analyze_file.qmsg
dds_using_FPGA/db/dds.asm.qmsg
dds_using_FPGA/db/dds.cbx.xml
dds_using_FPGA/db/dds.cmp.kpt
dds_using_FPGA/db/dds.cmp.rdb
dds_using_FPGA/db/dds.dbp
dds_using_FPGA/db/dds.db_info
dds_using_FPGA/db/dds.eco.cdb
dds_using_FPGA/db/dds.fit.qmsg
dds_using_FPGA/db/dds.hier_info
dds_using_FPGA/db/dds.hif
dds_using_FPGA/db/dds.map.hdb
dds_using_FPGA/db/dds.map.logdb
dds_using_FPGA/db/dds.map.qmsg
dds_using_FPGA/db/dds.pre_map.hdb
dds_using_FPGA/db/dds.psp
dds_using_FPGA/db/dds.rtlv.hdb
dds_using_FPGA/db/dds.rtlv_sg.cdb
dds_using_FPGA/db/dds.rtlv_sg_swap.cdb
dds_using_FPGA/db/dds.sgdiff.cdb
dds_using_FPGA/db/dds.sgdiff.hdb
dds_using_FPGA/db/dds.sld_design_entry.sci
dds_using_FPGA/db/dds.sld_design_entry_dsc.sci
dds_using_FPGA/db/dds.syn_hier_info
d
dds_using_FPGA/cos_rom.bsf
dds_using_FPGA/cos_rom.inc
dds_using_FPGA/cos_rom.tdf
dds_using_FPGA/dds.asm.rpt
dds_using_FPGA/dds.done
dds_using_FPGA/dds.fit.rpt
dds_using_FPGA/dds.fit.smsg
dds_using_FPGA/dds.fit.summary
dds_using_FPGA/dds.flow.rpt
dds_using_FPGA/dds.map.rpt
dds_using_FPGA/dds.map.summary
dds_using_FPGA/dds.pin
dds_using_FPGA/dds.qpf
dds_using_FPGA/dds.qsf
dds_using_FPGA/dds.qws
dds_using_FPGA/dds.tan.rpt
dds_using_FPGA/dds.tan.summary
dds_using_FPGA/dds_lut.bdf
dds_using_FPGA/dds_lut.bsf
dds_using_FPGA/dds_lut.v
dds_using_FPGA/mux4.bsf
dds_using_FPGA/mux4.inc
dds_using_FPGA/mux4.tdf
dds_using_FPGA/ram.bsf
dds_using_FPGA/ram.inc
dds_using_FPGA/ram.tdf
dds_using_FPGA/sin.mif
dds_using_FPGA/sin_rom.bsf
dds_using_FPGA/sin_rom.inc
dds_using_FPGA/sin_rom.tdf
dds_using_FPGA/square.bsf
dds_using_FPGA/square.inc
dds_using_FPGA/square.tdf
dds_using_FPGA/squra.mif
dds_using_FPGA/db/add_sub_6fg.tdf
dds_using_FPGA/db/altsyncram_3u41.tdf
dds_using_FPGA/db/altsyncram_4pi2.tdf
dds_using_FPGA/db/altsyncram_90m1.tdf
dds_using_FPGA/db/altsyncram_9pi2.tdf
dds_using_FPGA/db/altsyncram_b431.tdf
dds_using_FPGA/db/altsyncram_ut41.tdf
dds_using_FPGA/db/altsyncram_vpl1.tdf
dds_using_FPGA/db/dds.(0).cnf.cdb
dds_using_FPGA/db/dds.(0).cnf.hdb
dds_using_FPGA/db/dds.(1).cnf.cdb
dds_using_FPGA/db/dds.(1).cnf.hdb
dds_using_FPGA/db/dds.(10).cnf.cdb
dds_using_FPGA/db/dds.(10).cnf.hdb
dds_using_FPGA/db/dds.(11).cnf.cdb
dds_using_FPGA/db/dds.(11).cnf.hdb
dds_using_FPGA/db/dds.(12).cnf.cdb
dds_using_FPGA/db/dds.(12).cnf.hdb
dds_using_FPGA/db/dds.(13).cnf.cdb
dds_using_FPGA/db/dds.(13).cnf.hdb
dds_using_FPGA/db/dds.(14).cnf.cdb
dds_using_FPGA/db/dds.(14).cnf.hdb
dds_using_FPGA/db/dds.(15).cnf.cdb
dds_using_FPGA/db/dds.(15).cnf.hdb
dds_using_FPGA/db/dds.(16).cnf.cdb
dds_using_FPGA/db/dds.(16).cnf.hdb
dds_using_FPGA/db/dds.(17).cnf.cdb
dds_using_FPGA/db/dds.(17).cnf.hdb
dds_using_FPGA/db/dds.(18).cnf.cdb
dds_using_FPGA/db/dds.(18).cnf.hdb
dds_using_FPGA/db/dds.(19).cnf.cdb
dds_using_FPGA/db/dds.(19).cnf.hdb
dds_using_FPGA/db/dds.(2).cnf.cdb
dds_using_FPGA/db/dds.(2).cnf.hdb
dds_using_FPGA/db/dds.(20).cnf.cdb
dds_using_FPGA/db/dds.(20).cnf.hdb
dds_using_FPGA/db/dds.(21).cnf.cdb
dds_using_FPGA/db/dds.(21).cnf.hdb
dds_using_FPGA/db/dds.(22).cnf.cdb
dds_using_FPGA/db/dds.(22).cnf.hdb
dds_using_FPGA/db/dds.(23).cnf.cdb
dds_using_FPGA/db/dds.(23).cnf.hdb
dds_using_FPGA/db/dds.(24).cnf.cdb
dds_using_FPGA/db/dds.(24).cnf.hdb
dds_using_FPGA/db/dds.(25).cnf.cdb
dds_using_FPGA/db/dds.(25).cnf.hdb
dds_using_FPGA/db/dds.(26).cnf.cdb
dds_using_FPGA/db/dds.(26).cnf.hdb
dds_using_FPGA/db/dds.(27).cnf.cdb
dds_using_FPGA/db/dds.(27).cnf.hdb
dds_using_FPGA/db/dds.(28).cnf.cdb
dds_using_FPGA/db/dds.(28).cnf.hdb
dds_using_FPGA/db/dds.(29).cnf.cdb
dds_using_FPGA/db/dds.(29).cnf.hdb
dds_using_FPGA/db/dds.(3).cnf.cdb
dds_using_FPGA/db/dds.(3).cnf.hdb
dds_using_FPGA/db/dds.(30).cnf.cdb
dds_using_FPGA/db/dds.(30).cnf.hdb
dds_using_FPGA/db/dds.(31).cnf.cdb
dds_using_FPGA/db/dds.(31).cnf.hdb
dds_using_FPGA/db/dds.(32).cnf.cdb
dds_using_FPGA/db/dds.(32).cnf.hdb
dds_using_FPGA/db/dds.(33).cnf.cdb
dds_using_FPGA/db/dds.(33).cnf.hdb
dds_using_FPGA/db/dds.(34).cnf.cdb
dds_using_FPGA/db/dds.(34).cnf.hdb
dds_using_FPGA/db/dds.(35).cnf.cdb
dds_using_FPGA/db/dds.(35).cnf.hdb
dds_using_FPGA/db/dds.(36).cnf.cdb
dds_using_FPGA/db/dds.(36).cnf.hdb
dds_using_FPGA/db/dds.(37).cnf.cdb
dds_using_FPGA/db/dds.(37).cnf.hdb
dds_using_FPGA/db/dds.(38).cnf.cdb
dds_using_FPGA/db/dds.(38).cnf.hdb
dds_using_FPGA/db/dds.(39).cnf.cdb
dds_using_FPGA/db/dds.(39).cnf.hdb
dds_using_FPGA/db/dds.(4).cnf.cdb
dds_using_FPGA/db/dds.(4).cnf.hdb
dds_using_FPGA/db/dds.(40).cnf.cdb
dds_using_FPGA/db/dds.(40).cnf.hdb
dds_using_FPGA/db/dds.(41).cnf.cdb
dds_using_FPGA/db/dds.(41).cnf.hdb
dds_using_FPGA/db/dds.(42).cnf.cdb
dds_using_FPGA/db/dds.(42).cnf.hdb
dds_using_FPGA/db/dds.(43).cnf.cdb
dds_using_FPGA/db/dds.(43).cnf.hdb
dds_using_FPGA/db/dds.(44).cnf.cdb
dds_using_FPGA/db/dds.(44).cnf.hdb
dds_using_FPGA/db/dds.(5).cnf.cdb
dds_using_FPGA/db/dds.(5).cnf.hdb
dds_using_FPGA/db/dds.(6).cnf.cdb
dds_using_FPGA/db/dds.(6).cnf.hdb
dds_using_FPGA/db/dds.(7).cnf.cdb
dds_using_FPGA/db/dds.(7).cnf.hdb
dds_using_FPGA/db/dds.(8).cnf.cdb
dds_using_FPGA/db/dds.(8).cnf.hdb
dds_using_FPGA/db/dds.(9).cnf.cdb
dds_using_FPGA/db/dds.(9).cnf.hdb
dds_using_FPGA/db/dds.analyze_file.qmsg
dds_using_FPGA/db/dds.asm.qmsg
dds_using_FPGA/db/dds.cbx.xml
dds_using_FPGA/db/dds.cmp.kpt
dds_using_FPGA/db/dds.cmp.rdb
dds_using_FPGA/db/dds.dbp
dds_using_FPGA/db/dds.db_info
dds_using_FPGA/db/dds.eco.cdb
dds_using_FPGA/db/dds.fit.qmsg
dds_using_FPGA/db/dds.hier_info
dds_using_FPGA/db/dds.hif
dds_using_FPGA/db/dds.map.hdb
dds_using_FPGA/db/dds.map.logdb
dds_using_FPGA/db/dds.map.qmsg
dds_using_FPGA/db/dds.pre_map.hdb
dds_using_FPGA/db/dds.psp
dds_using_FPGA/db/dds.rtlv.hdb
dds_using_FPGA/db/dds.rtlv_sg.cdb
dds_using_FPGA/db/dds.rtlv_sg_swap.cdb
dds_using_FPGA/db/dds.sgdiff.cdb
dds_using_FPGA/db/dds.sgdiff.hdb
dds_using_FPGA/db/dds.sld_design_entry.sci
dds_using_FPGA/db/dds.sld_design_entry_dsc.sci
dds_using_FPGA/db/dds.syn_hier_info
d
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