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文件名称:VIRTUAL INPUT OUTPUT VERILOG CODE

  • 所属分类：
    VHDL编程
  • 标签属性：
    [VHDL] [源码]
  • 上传时间：
    2024-10-14
  • 文件大小：
    6.5mb
  • 已下载：
    0次
  • 提 供 者：
    diptanshumalv*************
  • 相关连接：
    无
  • 下载说明：
    别用迅雷下载，失败请重下，重下不扣分！
修正介绍说明

介绍说明－－下载内容来自于网络，使用问题请自行百度

THE IS CODE THAT USED THE VERILOG WHERE VIO FUNCTION USED
(系统自动生成,下载前可以参看下载内容)

下载文件列表

压缩包 : adder_VIO.rar 列表
adder_VIO/adder_VIO.cache/ip/2022.2/4/1/411f2c6c290c6a44/411f2c6c290c6a44.xci
adder_VIO/adder_VIO.cache/ip/2022.2/4/1/411f2c6c290c6a44/design_adder_adder_8_0_0.dcp
adder_VIO/adder_VIO.cache/ip/2022.2/4/1/411f2c6c290c6a44/design_adder_adder_8_0_0_sim_netlist.v
adder_VIO/adder_VIO.cache/ip/2022.2/4/1/411f2c6c290c6a44/design_adder_adder_8_0_0_sim_netlist.vhdl
adder_VIO/adder_VIO.cache/ip/2022.2/4/1/411f2c6c290c6a44/design_adder_adder_8_0_0_stub.v
adder_VIO/adder_VIO.cache/ip/2022.2/4/1/411f2c6c290c6a44/design_adder_adder_8_0_0_stub.vhdl
adder_VIO/adder_VIO.cache/ip/2022.2/5/6/5607b20cf845fa27/5607b20cf845fa27.xci
adder_VIO/adder_VIO.cache/ip/2022.2/5/6/5607b20cf845fa27/design_adder_vio_0_0.dcp
adder_VIO/adder_VIO.cache/ip/2022.2/5/6/5607b20cf845fa27/design_adder_vio_0_0_sim_netlist.v
adder_VIO/adder_VIO.cache/ip/2022.2/5/6/5607b20cf845fa27/design_adder_vio_0_0_sim_netlist.vhdl
adder_VIO/adder_VIO.cache/ip/2022.2/5/6/5607b20cf845fa27/design_adder_vio_0_0_stub.v
adder_VIO/adder_VIO.cache/ip/2022.2/5/6/5607b20cf845fa27/design_adder_vio_0_0_stub.vhdl
adder_VIO/adder_VIO.cache/sim/ssm.db
adder_VIO/adder_VIO.cache/wt/project.wpc
adder_VIO/adder_VIO.cache/wt/synthesis.wdf
adder_VIO/adder_VIO.cache/wt/synthesis_details.wdf
adder_VIO/adder_VIO.cache/wt/webtalk_pa.xml
adder_VIO/adder_VIO.cache/wt/xsim.wdf
adder_VIO/adder_VIO.gen/sources_1/bd/design_adder/design_adder.bda
adder_VIO/adder_VIO.gen/sources_1/bd/design_adder/design_adder.bxml
adder_VIO/adder_VIO.gen/sources_1/bd/design_adder/design_adder_ooc.xdc
adder_VIO/adder_VIO.gen/sources_1/bd/design_adder/hdl/design_adder_wrapper.v
adder_VIO/adder_VIO.gen/sources_1/bd/design_adder/hw_handoff/design_adder.hwh
adder_VIO/adder_VIO.gen/sources_1/bd/design_adder/ip/design_adder_adder_8_0_0/design_adder_adder_8_0_0.dcp
adder_VIO/adder_VIO.gen/sources_1/bd/design_adder/ip/design_adder_adder_8_0_0/design_adder_adder_8_0_0.xml
adder_VIO/adder_VIO.gen/sources_1/bd/design_adder/ip/design_adder_adder_8_0_0/design_adder_adder_8_0_0_sim_netlist.v
adder_VIO/adder_VIO.gen/sources_1/bd/design_adder/ip/design_adder_adder_8_0_0/design_adder_adder_8_0_0_sim_netlist.vhdl
adder_VIO/adder_VIO.gen/sources_1/bd/design_adder/ip/design_adder_adder_8_0_0/design_adder_adder_8_0_0_stub.v
adder_VIO/adder_VIO.gen/sources_1/bd/design_adder/ip/design_adder_adder_8_0_0/design_adder_adder_8_0_0_stub.vhdl
adder_VIO/adder_VIO.gen/sources_1/bd/design_adder/ip/design_adder_adder_8_0_0/sim/design_adder_adder_8_0_0.v
adder_VIO/adder_VIO.gen/sources_1/bd/design_adder/ip/design_adder_adder_8_0_0/synth/design_adder_adder_8_0_0.v
adder_VIO/adder_VIO.gen/sources_1/bd/design_adder/ip/design_adder_vio_0_0/design_adder_vio_0_0.dcp
adder_VIO/adder_VIO.gen/sources_1/bd/design_adder/ip/design_adder_vio_0_0/design_adder_vio_0_0.xdc
adder_VIO/adder_VIO.gen/sources_1/bd/design_adder/ip/design_adder_vio_0_0/design_adder_vio_0_0.xml
adder_VIO/adder_VIO.gen/sources_1/bd/design_adder/ip/design_adder_vio_0_0/design_adder_vio_0_0_ooc.xdc
adder_VIO/adder_VIO.gen/sources_1/bd/design_adder/ip/design_adder_vio_0_0/design_adder_vio_0_0_sim_netlist.v
adder_VIO/adder_VIO.gen/sources_1/bd/design_adder/ip/design_adder_vio_0_0/design_adder_vio_0_0_sim_netlist.vhdl
adder_VIO/adder_VIO.gen/sources_1/bd/design_adder/ip/design_adder_vio_0_0/design_adder_vio_0_0_stub.v
adder_VIO/adder_VIO.gen/sources_1/bd/design_adder/ip/design_adder_vio_0_0/design_adder_vio_0_0_stub.vhdl
adder_VIO/adder_VIO.gen/sources_1/bd/design_adder/ip/design_adder_vio_0_0/sim/design_adder_vio_0_0.v
adder_VIO/adder_VIO.gen/sources_1/bd/design_adder/ip/design_adder_vio_0_0/synth/design_adder_vio_0_0.v
adder_VIO/adder_VIO.gen/sources_1/bd/design_adder/ipshared/122e/hdl/verilog/xsdbs_v1_0_2_i2x.vh
adder_VIO/adder_VIO.gen/sources_1/bd/design_adder/ipshared/122e/hdl/verilog/xsdbs_v1_0_2_in.vh
adder_VIO/adder_VIO.gen/sources_1/bd/design_adder/ipshared/122e/hdl/xsdbs_v1_0_vl_rfs.v
adder_VIO/adder_VIO.gen/sources_1/bd/design_adder/ipshared/1b7e/hdl/ltlib_v1_0_vl_rfs.v
adder_VIO/adder_VIO.gen/sources_

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