今天看了一下从fpga上下的曼彻斯特编解码的程序，感觉不是很清楚，仿真了一下，更迷茫了，大家看看为啥这程序要这么编呢？

程序比较长，不过写的应该还是不错的，看了后应该有收获。

总的思路是这样：

1 通过一个高频的时钟检测wrn信号，如果检测到上升沿，则表明开始编码，将输入的8位数据转为串行，并编码，然后输出。

2 定时信号是从高频时钟16分频后得到的，在wrn上升沿后16分频使能，在编码结束后禁止分频输出。

3 no_bits_sent记录串行输出的位数，应该是从0010到1001输出串行信号，到1010时编码结束，输出tbre表明编码完成。

问题是no_bits_sent在到了1010后还是会继续增加，直到1111，然后clk1x_enable 就为0，无法分频，clk1x就为一直流信号。这样当clk1x_enable再次为1的时候，no_bits_sent也不会增加，在1111上不变，clk1x_enable又会回到0了。

-today they simply watched from across the Manchester encoding and decoding process, not feeling very well, simulation a bit more confused, we look at procedures to be ready this series so? Procedures longer, but should still write good, it should have read harvest. The thinking is this : one by a high-frequency clock signal detection international, if detected rising edge, it indicates the beginning of coding will be entered into the eight to serial data and coding, and then output. Two timing signals from the high-frequency clock frequency 16 hours after the the international rising edge after 16 minutes frequency to enable the coding after the end of Prohibition-frequency output. 3 no_bits_sent record median serial output, it should be from 0010 to 1001 serial output signal to the end of