文件名称:usb1_funct
介绍说明--下载内容来自于网络,使用问题请自行百度
usb设备端源代码,包括测试平台和文档。
(系统自动生成,下载前可以参看下载内容)
下载文件列表
usb1_funct/bench/CVS/Entries
usb1_funct/bench/CVS/Entries.Extra
usb1_funct/bench/CVS/Entries.Extra.Old
usb1_funct/bench/CVS/Entries.Old
usb1_funct/bench/CVS/Repository
usb1_funct/bench/CVS/Root
usb1_funct/bench/CVS/Template
usb1_funct/bench/verilog/CVS/Entries
usb1_funct/bench/verilog/CVS/Entries.Extra
usb1_funct/bench/verilog/CVS/Entries.Extra.Old
usb1_funct/bench/verilog/CVS/Entries.Old
usb1_funct/bench/verilog/CVS/Repository
usb1_funct/bench/verilog/CVS/Root
usb1_funct/bench/verilog/CVS/Template
usb1_funct/bench/verilog/tests.v
usb1_funct/bench/verilog/tests_lib.v
usb1_funct/bench/verilog/test_bench_top.v
usb1_funct/bench/verilog/timescale.v
usb1_funct/CVS/Entries
usb1_funct/CVS/Entries.Extra
usb1_funct/CVS/Entries.Extra.Old
usb1_funct/CVS/Entries.Log
usb1_funct/CVS/Entries.Old
usb1_funct/CVS/Repository
usb1_funct/CVS/Root
usb1_funct/CVS/Template
usb1_funct/doc/CVS/Entries
usb1_funct/doc/CVS/Entries.Extra
usb1_funct/doc/CVS/Entries.Extra.Old
usb1_funct/doc/CVS/Entries.Old
usb1_funct/doc/CVS/Repository
usb1_funct/doc/CVS/Root
usb1_funct/doc/CVS/Template
usb1_funct/doc/README.txt
usb1_funct/doc/success_story.txt
usb1_funct/rtl/CVS/Entries
usb1_funct/rtl/CVS/Entries.Extra
usb1_funct/rtl/CVS/Entries.Extra.Old
usb1_funct/rtl/CVS/Entries.Old
usb1_funct/rtl/CVS/Repository
usb1_funct/rtl/CVS/Root
usb1_funct/rtl/CVS/Template
usb1_funct/rtl/verilog/CVS/Entries
usb1_funct/rtl/verilog/CVS/Entries.Extra
usb1_funct/rtl/verilog/CVS/Entries.Extra.Old
usb1_funct/rtl/verilog/CVS/Entries.Old
usb1_funct/rtl/verilog/CVS/Repository
usb1_funct/rtl/verilog/CVS/Root
usb1_funct/rtl/verilog/CVS/Template
usb1_funct/rtl/verilog/timescale.v
usb1_funct/rtl/verilog/usb1_core.v
usb1_funct/rtl/verilog/usb1_crc16.v
usb1_funct/rtl/verilog/usb1_crc5.v
usb1_funct/rtl/verilog/usb1_ctrl.v
usb1_funct/rtl/verilog/usb1_defines.v
usb1_funct/rtl/verilog/usb1_fifo2.v
usb1_funct/rtl/verilog/usb1_idma.v
usb1_funct/rtl/verilog/usb1_pa.v
usb1_funct/rtl/verilog/usb1_pd.v
usb1_funct/rtl/verilog/usb1_pe.v
usb1_funct/rtl/verilog/usb1_pl.v
usb1_funct/rtl/verilog/usb1_rom1.v
usb1_funct/rtl/verilog/usb1_utmi_if.v
usb1_funct/sim/CVS/Entries
usb1_funct/sim/CVS/Entries.Extra
usb1_funct/sim/CVS/Entries.Extra.Old
usb1_funct/sim/CVS/Entries.Old
usb1_funct/sim/CVS/Repository
usb1_funct/sim/CVS/Root
usb1_funct/sim/CVS/Template
usb1_funct/sim/rtl_sim/bin/CVS/Entries
usb1_funct/sim/rtl_sim/bin/CVS/Entries.Extra
usb1_funct/sim/rtl_sim/bin/CVS/Entries.Extra.Old
usb1_funct/sim/rtl_sim/bin/CVS/Entries.Old
usb1_funct/sim/rtl_sim/bin/CVS/Repository
usb1_funct/sim/rtl_sim/bin/CVS/Root
usb1_funct/sim/rtl_sim/bin/CVS/Template
usb1_funct/sim/rtl_sim/bin/Makefile
usb1_funct/sim/rtl_sim/CVS/Entries
usb1_funct/sim/rtl_sim/CVS/Entries.Extra
usb1_funct/sim/rtl_sim/CVS/Entries.Extra.Old
usb1_funct/sim/rtl_sim/CVS/Entries.Log
usb1_funct/sim/rtl_sim/CVS/Entries.Old
usb1_funct/sim/rtl_sim/CVS/Repository
usb1_funct/sim/rtl_sim/CVS/Root
usb1_funct/sim/rtl_sim/CVS/Template
usb1_funct/sim/rtl_sim/run/CVS/Entries
usb1_funct/sim/rtl_sim/run/CVS/Entries.Extra
usb1_funct/sim/rtl_sim/run/CVS/Entries.Extra.Old
usb1_funct/sim/rtl_sim/run/CVS/Entries.Old
usb1_funct/sim/rtl_sim/run/CVS/Repository
usb1_funct/sim/rtl_sim/run/CVS/Root
usb1_funct/sim/rtl_sim/run/CVS/Template
usb1_funct/sim/rtl_sim/run/Makefile
usb1_funct/sim/rtl_sim/run/waves/CVS/Entries
usb1_funct/sim/rtl_sim/run/waves/CVS/Entries.Extra
usb1_funct/sim/rtl_sim/run/waves/CVS/Entries.Extra.Old
usb1_funct/sim/rtl_sim/run/waves/CVS/Entries.Old
usb1_funct/sim/rtl_sim/run/waves/CVS/Repository
usb1_funct/sim/rtl_sim/run/waves/CVS/Root
usb1_funct/sim/rtl_sim/run/waves/CVS/Template
usb1_funct/sim/rtl_sim/run/waves/waves.do
usb1_funct/sim/rtl_sim/run/waves/CVS
usb1_funct/sim/rtl_sim/bin/CVS
usb1_funct/sim/rtl_sim/run/CVS
usb1_funct/sim/rtl_sim/run/waves
usb1_funct/bench/verilog/CVS
usb1_funct/rtl/verilog/CVS
usb1_funct/sim/rtl_sim/bin
usb1_funct/sim/rtl_sim/CVS
usb1_funct/sim/rtl_sim/run
usb1_funct/bench/CVS
usb1_funct/bench/verilog
usb1_funct/doc/CVS
usb1_funct/rtl/CVS
usb1_funct/rtl/verilog
usb1_funct/sim/CVS
usb1_funct/sim/rtl_sim
usb1_funct/bench
usb1_funct/CVS
usb1_funct/doc
usb1_funct/rtl
usb1_funct/sim
usb1_funct
www.dssz.com.txt
usb1_funct/bench/CVS/Entries.Extra
usb1_funct/bench/CVS/Entries.Extra.Old
usb1_funct/bench/CVS/Entries.Old
usb1_funct/bench/CVS/Repository
usb1_funct/bench/CVS/Root
usb1_funct/bench/CVS/Template
usb1_funct/bench/verilog/CVS/Entries
usb1_funct/bench/verilog/CVS/Entries.Extra
usb1_funct/bench/verilog/CVS/Entries.Extra.Old
usb1_funct/bench/verilog/CVS/Entries.Old
usb1_funct/bench/verilog/CVS/Repository
usb1_funct/bench/verilog/CVS/Root
usb1_funct/bench/verilog/CVS/Template
usb1_funct/bench/verilog/tests.v
usb1_funct/bench/verilog/tests_lib.v
usb1_funct/bench/verilog/test_bench_top.v
usb1_funct/bench/verilog/timescale.v
usb1_funct/CVS/Entries
usb1_funct/CVS/Entries.Extra
usb1_funct/CVS/Entries.Extra.Old
usb1_funct/CVS/Entries.Log
usb1_funct/CVS/Entries.Old
usb1_funct/CVS/Repository
usb1_funct/CVS/Root
usb1_funct/CVS/Template
usb1_funct/doc/CVS/Entries
usb1_funct/doc/CVS/Entries.Extra
usb1_funct/doc/CVS/Entries.Extra.Old
usb1_funct/doc/CVS/Entries.Old
usb1_funct/doc/CVS/Repository
usb1_funct/doc/CVS/Root
usb1_funct/doc/CVS/Template
usb1_funct/doc/README.txt
usb1_funct/doc/success_story.txt
usb1_funct/rtl/CVS/Entries
usb1_funct/rtl/CVS/Entries.Extra
usb1_funct/rtl/CVS/Entries.Extra.Old
usb1_funct/rtl/CVS/Entries.Old
usb1_funct/rtl/CVS/Repository
usb1_funct/rtl/CVS/Root
usb1_funct/rtl/CVS/Template
usb1_funct/rtl/verilog/CVS/Entries
usb1_funct/rtl/verilog/CVS/Entries.Extra
usb1_funct/rtl/verilog/CVS/Entries.Extra.Old
usb1_funct/rtl/verilog/CVS/Entries.Old
usb1_funct/rtl/verilog/CVS/Repository
usb1_funct/rtl/verilog/CVS/Root
usb1_funct/rtl/verilog/CVS/Template
usb1_funct/rtl/verilog/timescale.v
usb1_funct/rtl/verilog/usb1_core.v
usb1_funct/rtl/verilog/usb1_crc16.v
usb1_funct/rtl/verilog/usb1_crc5.v
usb1_funct/rtl/verilog/usb1_ctrl.v
usb1_funct/rtl/verilog/usb1_defines.v
usb1_funct/rtl/verilog/usb1_fifo2.v
usb1_funct/rtl/verilog/usb1_idma.v
usb1_funct/rtl/verilog/usb1_pa.v
usb1_funct/rtl/verilog/usb1_pd.v
usb1_funct/rtl/verilog/usb1_pe.v
usb1_funct/rtl/verilog/usb1_pl.v
usb1_funct/rtl/verilog/usb1_rom1.v
usb1_funct/rtl/verilog/usb1_utmi_if.v
usb1_funct/sim/CVS/Entries
usb1_funct/sim/CVS/Entries.Extra
usb1_funct/sim/CVS/Entries.Extra.Old
usb1_funct/sim/CVS/Entries.Old
usb1_funct/sim/CVS/Repository
usb1_funct/sim/CVS/Root
usb1_funct/sim/CVS/Template
usb1_funct/sim/rtl_sim/bin/CVS/Entries
usb1_funct/sim/rtl_sim/bin/CVS/Entries.Extra
usb1_funct/sim/rtl_sim/bin/CVS/Entries.Extra.Old
usb1_funct/sim/rtl_sim/bin/CVS/Entries.Old
usb1_funct/sim/rtl_sim/bin/CVS/Repository
usb1_funct/sim/rtl_sim/bin/CVS/Root
usb1_funct/sim/rtl_sim/bin/CVS/Template
usb1_funct/sim/rtl_sim/bin/Makefile
usb1_funct/sim/rtl_sim/CVS/Entries
usb1_funct/sim/rtl_sim/CVS/Entries.Extra
usb1_funct/sim/rtl_sim/CVS/Entries.Extra.Old
usb1_funct/sim/rtl_sim/CVS/Entries.Log
usb1_funct/sim/rtl_sim/CVS/Entries.Old
usb1_funct/sim/rtl_sim/CVS/Repository
usb1_funct/sim/rtl_sim/CVS/Root
usb1_funct/sim/rtl_sim/CVS/Template
usb1_funct/sim/rtl_sim/run/CVS/Entries
usb1_funct/sim/rtl_sim/run/CVS/Entries.Extra
usb1_funct/sim/rtl_sim/run/CVS/Entries.Extra.Old
usb1_funct/sim/rtl_sim/run/CVS/Entries.Old
usb1_funct/sim/rtl_sim/run/CVS/Repository
usb1_funct/sim/rtl_sim/run/CVS/Root
usb1_funct/sim/rtl_sim/run/CVS/Template
usb1_funct/sim/rtl_sim/run/Makefile
usb1_funct/sim/rtl_sim/run/waves/CVS/Entries
usb1_funct/sim/rtl_sim/run/waves/CVS/Entries.Extra
usb1_funct/sim/rtl_sim/run/waves/CVS/Entries.Extra.Old
usb1_funct/sim/rtl_sim/run/waves/CVS/Entries.Old
usb1_funct/sim/rtl_sim/run/waves/CVS/Repository
usb1_funct/sim/rtl_sim/run/waves/CVS/Root
usb1_funct/sim/rtl_sim/run/waves/CVS/Template
usb1_funct/sim/rtl_sim/run/waves/waves.do
usb1_funct/sim/rtl_sim/run/waves/CVS
usb1_funct/sim/rtl_sim/bin/CVS
usb1_funct/sim/rtl_sim/run/CVS
usb1_funct/sim/rtl_sim/run/waves
usb1_funct/bench/verilog/CVS
usb1_funct/rtl/verilog/CVS
usb1_funct/sim/rtl_sim/bin
usb1_funct/sim/rtl_sim/CVS
usb1_funct/sim/rtl_sim/run
usb1_funct/bench/CVS
usb1_funct/bench/verilog
usb1_funct/doc/CVS
usb1_funct/rtl/CVS
usb1_funct/rtl/verilog
usb1_funct/sim/CVS
usb1_funct/sim/rtl_sim
usb1_funct/bench
usb1_funct/CVS
usb1_funct/doc
usb1_funct/rtl
usb1_funct/sim
usb1_funct
www.dssz.com.txt
本网站为编程资源及源代码搜集、介绍的搜索网站,版权归原作者所有! 粤ICP备11031372号
1999-2046 搜珍网 All Rights Reserved.