文件名称:uart
介绍说明--下载内容来自于网络,使用问题请自行百度
基于FPGA的uart控制器,波特率可选,VHDL编程,Quartusii 6.0 平台,vhdl语言编程
(系统自动生成,下载前可以参看下载内容)
下载文件列表
uart/uart程序说明.txt
uart/VHDLoo/uart_test/baud_rate.vhd
uart/VHDLoo/uart_test/cmp_state.ini
uart/VHDLoo/uart_test/CNT256.bsf
uart/VHDLoo/uart_test/CNT256.vhd
uart/VHDLoo/uart_test/fifo1.vhd
uart/VHDLoo/uart_test/filter.vhd
uart/VHDLoo/uart_test/parity_verifier.vhd
uart/VHDLoo/uart_test/receiver.vhd
uart/VHDLoo/uart_test/sinva.bsf
uart/VHDLoo/uart_test/sinva.cmp
uart/VHDLoo/uart_test/sinva.inc
uart/VHDLoo/uart_test/sinva.vhd
uart/VHDLoo/uart_test/transmitter.vhd
uart/VHDLoo/uart_test/uart_ctrl.vhd
uart/VHDLoo/uart_test/uart_package.vhd
uart/VHDLoo/uart_test/uart_test.asm.rpt
uart/VHDLoo/uart_test/uart_test.bsf
uart/VHDLoo/uart_test/uart_test.cdf
uart/VHDLoo/uart_test/uart_test.done
uart/VHDLoo/uart_test/uart_test.fit.eqn
uart/VHDLoo/uart_test/uart_test.fit.rpt
uart/VHDLoo/uart_test/uart_test.fit.summary
uart/VHDLoo/uart_test/uart_test.flow.rpt
uart/VHDLoo/uart_test/uart_test.map.eqn
uart/VHDLoo/uart_test/uart_test.map.rpt
uart/VHDLoo/uart_test/uart_test.map.summary
uart/VHDLoo/uart_test/uart_test.mif
uart/VHDLoo/uart_test/uart_test.pin
uart/VHDLoo/uart_test/uart_test.pof
uart/VHDLoo/uart_test/uart_test.qpf
uart/VHDLoo/uart_test/uart_test.qsf
uart/VHDLoo/uart_test/uart_test.qws
uart/VHDLoo/uart_test/uart_test.sof
uart/VHDLoo/uart_test/uart_test.tan.rpt
uart/VHDLoo/uart_test/uart_test.tan.summary
uart/VHDLoo/uart_test/uart_testb.bdf
uart/VHDLoo/uart_test/uart_testb.flow.rpt
uart/VHDLoo/uart_test/uart_testb.map.rpt
uart/VHDLoo/uart_test/uart_testb.map.summary
uart/VHDLoo/uart_test/uart_testb.qpf
uart/VHDLoo/uart_test/uart_testb.qsf
uart/VHDLoo/uart_test/uart_testb.qws
uart/VHDLoo/uart_test/uart_test_package.vhd
uart/VHDLoo/uart_test/uart_test.vhd
uart/VHDLoo/uart_test/db/altsyncram_cas.tdf
uart/VHDLoo/uart_test/db/altsyncram_m0a2.tdf
uart/VHDLoo/uart_test/db/altsyncram_vf31.tdf
uart/VHDLoo/uart_test/db/a_dpfifo_3rr.tdf
uart/VHDLoo/uart_test/db/cntr_bc7.tdf
uart/VHDLoo/uart_test/db/cntr_sd8.tdf
uart/VHDLoo/uart_test/db/cntr_td8.tdf
uart/VHDLoo/uart_test/db/decode_9ie.tdf
uart/VHDLoo/uart_test/db/scfifo_skr.tdf
uart/VHDLoo/uart_test/db/uart_test.map.qmsg
uart/VHDLoo/uart_test/db/uart_testb.db_info
uart/VHDLoo/uart_test/db/uart_test.eco.cdb
uart/VHDLoo/uart_test/db/uart_test.hif
uart/VHDLoo/uart_test/db/uart_testb.map.qmsg
uart/VHDLoo/uart_test/db/uart_testb.eco.cdb
uart/VHDLoo/uart_test/db/uart_testb.sld_design_entry_dsc.sci
uart/VHDLoo/uart_test/db/uart_testb.cbx.xml
uart/VHDLoo/uart_test/db/uart_testb.hif
uart/VHDLoo/uart_test/db/uart_testb.(0).cnf.cdb
uart/VHDLoo/uart_test/db/uart_testb.(0).cnf.hdb
uart/VHDLoo/uart_test/db/uart_testb.map.hdb
uart/VHDLoo/uart_test/db/uart_testb.cmp.rdb
uart/VHDLoo/uart_test/db/uart_testb.sld_design_entry.sci
uart/VHDLoo/uart_test/db/uart_test.sld_design_entry.sci
uart/VHDLoo/uart_test/db/uart_test.cbx.xml
uart/VHDLoo/uart_test/db/uart_test.sld_design_entry_dsc.sci
uart/VHDLoo/uart_test/db/uart_test.map.hdb
uart/VHDLoo/uart_test/db/uart_test.cmp.rdb
uart/VHDLoo/uart_test/db/uart_testb_cmp.qrpt
uart/VHDLoo/uart_test/db/uart_test_cmp.qrpt
uart/VHDLoo/uart_test/db/scfifo_okr.tdf
uart/VHDLoo/uart_test/db/a_dpfifo_vqr.tdf
uart/VHDLoo/uart_test/db/altsyncram_nf31.tdf
uart/VHDLoo/uart_test/db/cntr_cc7.tdf
uart/VHDLoo/uart_test/db/cntr_ud8.tdf
uart/VHDLoo/uart_test/db/uart_test.db_info
uart/VHDLoo/uart_test/db
uart/VHDLoo/uart_test/fifo1_waveforms.html
uart/VHDLoo/uart_test/fifo1_wave0.jpg
uart/VHDLoo/uart_test/fifo1.inc
uart/VHDLoo/uart_test/fifo1.cmp
uart/VHDLoo/uart_test/fifo1.bsf
uart/VHDLoo/uart_test/uart_test_assignment_defaults.qdf
uart/VHDLoo/uart_test/uart.bsf
uart/VHDLoo/uart_test/isme/uart_testb.map.talkback.xml
uart/VHDLoo/uart_test/isme/uart_testb.gui.talkback.xml
uart/VHDLoo/uart_test/isme/uart_test.map.talkback.xml
uart/VHDLoo/uart_test/isme/uart_test.gui.talkback.xml
uart/VHDLoo/uart_test/isme
uart/VHDLoo/uart_test/uart_testb_assignment_defaults.qdf
uart/VHDLoo/uart_test/filter.bsf
uart/VHDLoo/uart_test/uart_ctrl.bsf
uart/VHDLoo/uart_test/baud_rate.bsf
uart/VHDLoo/uart_test/receiver.bsf
uart/VHDLoo/uart_test/transmitter.bsf
uart/VHDLoo/uart_test/uart_ctr.bdf
uart/VHDLoo/uart_test/ctrl.vhd
uart/VHDLoo/uart_test/ctrl_uart.vhd
uart/VHDLoo/uart_test/ctrl_uart.bsf
uart/VHDLoo/uart_test/parity_verifier.bsf
uart/VHDLoo/uart_test/uart_ctr.bsf
uart/VHDLoo/uart_test/uart.bdf
uart/VHDLoo/uart_test
uart/VHDLoo/uart_ctrl/baud_rate.vhd
uart/VHDLoo/uart_ctrl/cmp_state.ini
uart/VHDLoo/uart_ctrl/fifo1.vhd
uart/VHDLoo/uart_ctrl/filter.vhd
uart/VHDLoo/uart_ctrl/parity_verifier.vhd
uart/VHDLoo/uart_ctrl/receiver.vhd
uart/VHDLoo/uart_ctrl/transmitter.vhd
uart/VHDLoo/uart_ctrl/uart_ctrl.asm.rpt
uart/VHDLoo/uart_ctrl/uart_ctrl.done
uart/VHDLoo/uart_ctrl/uart_ctrl.fit.eqn
uart/VHDLoo/uart_ctrl/uart_ctrl.fit.rpt
uart/VHDLoo/uart_ctrl/uart_ctrl.fit.summary
uart/VHDLoo/uart_ctrl/uart_ctrl.flow.rpt
uart/VHDLoo/uart_ctrl/uart_ctrl.map.eqn
uart/VHDLoo/uart_ctrl/uart_ctrl.map.rpt
uart/VHDLoo/uart_ctrl/uart_ctrl.map.summary
uart/VHDLoo/uart_ctrl/uart_ctrl.pin
uart/VHDLoo/uart_ctrl/uart_ctrl.pof
uart/VHDLoo/uart_ctrl/uart_ctrl.qpf
uart/VHDLoo/uart_ctrl/uart_ctrl.qsf
uart/VHDLoo/uart_ctrl/uart_ctrl.qws
uart/VHDLoo/uart_ctrl
uart/VHDLoo/uart_test/baud_rate.vhd
uart/VHDLoo/uart_test/cmp_state.ini
uart/VHDLoo/uart_test/CNT256.bsf
uart/VHDLoo/uart_test/CNT256.vhd
uart/VHDLoo/uart_test/fifo1.vhd
uart/VHDLoo/uart_test/filter.vhd
uart/VHDLoo/uart_test/parity_verifier.vhd
uart/VHDLoo/uart_test/receiver.vhd
uart/VHDLoo/uart_test/sinva.bsf
uart/VHDLoo/uart_test/sinva.cmp
uart/VHDLoo/uart_test/sinva.inc
uart/VHDLoo/uart_test/sinva.vhd
uart/VHDLoo/uart_test/transmitter.vhd
uart/VHDLoo/uart_test/uart_ctrl.vhd
uart/VHDLoo/uart_test/uart_package.vhd
uart/VHDLoo/uart_test/uart_test.asm.rpt
uart/VHDLoo/uart_test/uart_test.bsf
uart/VHDLoo/uart_test/uart_test.cdf
uart/VHDLoo/uart_test/uart_test.done
uart/VHDLoo/uart_test/uart_test.fit.eqn
uart/VHDLoo/uart_test/uart_test.fit.rpt
uart/VHDLoo/uart_test/uart_test.fit.summary
uart/VHDLoo/uart_test/uart_test.flow.rpt
uart/VHDLoo/uart_test/uart_test.map.eqn
uart/VHDLoo/uart_test/uart_test.map.rpt
uart/VHDLoo/uart_test/uart_test.map.summary
uart/VHDLoo/uart_test/uart_test.mif
uart/VHDLoo/uart_test/uart_test.pin
uart/VHDLoo/uart_test/uart_test.pof
uart/VHDLoo/uart_test/uart_test.qpf
uart/VHDLoo/uart_test/uart_test.qsf
uart/VHDLoo/uart_test/uart_test.qws
uart/VHDLoo/uart_test/uart_test.sof
uart/VHDLoo/uart_test/uart_test.tan.rpt
uart/VHDLoo/uart_test/uart_test.tan.summary
uart/VHDLoo/uart_test/uart_testb.bdf
uart/VHDLoo/uart_test/uart_testb.flow.rpt
uart/VHDLoo/uart_test/uart_testb.map.rpt
uart/VHDLoo/uart_test/uart_testb.map.summary
uart/VHDLoo/uart_test/uart_testb.qpf
uart/VHDLoo/uart_test/uart_testb.qsf
uart/VHDLoo/uart_test/uart_testb.qws
uart/VHDLoo/uart_test/uart_test_package.vhd
uart/VHDLoo/uart_test/uart_test.vhd
uart/VHDLoo/uart_test/db/altsyncram_cas.tdf
uart/VHDLoo/uart_test/db/altsyncram_m0a2.tdf
uart/VHDLoo/uart_test/db/altsyncram_vf31.tdf
uart/VHDLoo/uart_test/db/a_dpfifo_3rr.tdf
uart/VHDLoo/uart_test/db/cntr_bc7.tdf
uart/VHDLoo/uart_test/db/cntr_sd8.tdf
uart/VHDLoo/uart_test/db/cntr_td8.tdf
uart/VHDLoo/uart_test/db/decode_9ie.tdf
uart/VHDLoo/uart_test/db/scfifo_skr.tdf
uart/VHDLoo/uart_test/db/uart_test.map.qmsg
uart/VHDLoo/uart_test/db/uart_testb.db_info
uart/VHDLoo/uart_test/db/uart_test.eco.cdb
uart/VHDLoo/uart_test/db/uart_test.hif
uart/VHDLoo/uart_test/db/uart_testb.map.qmsg
uart/VHDLoo/uart_test/db/uart_testb.eco.cdb
uart/VHDLoo/uart_test/db/uart_testb.sld_design_entry_dsc.sci
uart/VHDLoo/uart_test/db/uart_testb.cbx.xml
uart/VHDLoo/uart_test/db/uart_testb.hif
uart/VHDLoo/uart_test/db/uart_testb.(0).cnf.cdb
uart/VHDLoo/uart_test/db/uart_testb.(0).cnf.hdb
uart/VHDLoo/uart_test/db/uart_testb.map.hdb
uart/VHDLoo/uart_test/db/uart_testb.cmp.rdb
uart/VHDLoo/uart_test/db/uart_testb.sld_design_entry.sci
uart/VHDLoo/uart_test/db/uart_test.sld_design_entry.sci
uart/VHDLoo/uart_test/db/uart_test.cbx.xml
uart/VHDLoo/uart_test/db/uart_test.sld_design_entry_dsc.sci
uart/VHDLoo/uart_test/db/uart_test.map.hdb
uart/VHDLoo/uart_test/db/uart_test.cmp.rdb
uart/VHDLoo/uart_test/db/uart_testb_cmp.qrpt
uart/VHDLoo/uart_test/db/uart_test_cmp.qrpt
uart/VHDLoo/uart_test/db/scfifo_okr.tdf
uart/VHDLoo/uart_test/db/a_dpfifo_vqr.tdf
uart/VHDLoo/uart_test/db/altsyncram_nf31.tdf
uart/VHDLoo/uart_test/db/cntr_cc7.tdf
uart/VHDLoo/uart_test/db/cntr_ud8.tdf
uart/VHDLoo/uart_test/db/uart_test.db_info
uart/VHDLoo/uart_test/db
uart/VHDLoo/uart_test/fifo1_waveforms.html
uart/VHDLoo/uart_test/fifo1_wave0.jpg
uart/VHDLoo/uart_test/fifo1.inc
uart/VHDLoo/uart_test/fifo1.cmp
uart/VHDLoo/uart_test/fifo1.bsf
uart/VHDLoo/uart_test/uart_test_assignment_defaults.qdf
uart/VHDLoo/uart_test/uart.bsf
uart/VHDLoo/uart_test/isme/uart_testb.map.talkback.xml
uart/VHDLoo/uart_test/isme/uart_testb.gui.talkback.xml
uart/VHDLoo/uart_test/isme/uart_test.map.talkback.xml
uart/VHDLoo/uart_test/isme/uart_test.gui.talkback.xml
uart/VHDLoo/uart_test/isme
uart/VHDLoo/uart_test/uart_testb_assignment_defaults.qdf
uart/VHDLoo/uart_test/filter.bsf
uart/VHDLoo/uart_test/uart_ctrl.bsf
uart/VHDLoo/uart_test/baud_rate.bsf
uart/VHDLoo/uart_test/receiver.bsf
uart/VHDLoo/uart_test/transmitter.bsf
uart/VHDLoo/uart_test/uart_ctr.bdf
uart/VHDLoo/uart_test/ctrl.vhd
uart/VHDLoo/uart_test/ctrl_uart.vhd
uart/VHDLoo/uart_test/ctrl_uart.bsf
uart/VHDLoo/uart_test/parity_verifier.bsf
uart/VHDLoo/uart_test/uart_ctr.bsf
uart/VHDLoo/uart_test/uart.bdf
uart/VHDLoo/uart_test
uart/VHDLoo/uart_ctrl/baud_rate.vhd
uart/VHDLoo/uart_ctrl/cmp_state.ini
uart/VHDLoo/uart_ctrl/fifo1.vhd
uart/VHDLoo/uart_ctrl/filter.vhd
uart/VHDLoo/uart_ctrl/parity_verifier.vhd
uart/VHDLoo/uart_ctrl/receiver.vhd
uart/VHDLoo/uart_ctrl/transmitter.vhd
uart/VHDLoo/uart_ctrl/uart_ctrl.asm.rpt
uart/VHDLoo/uart_ctrl/uart_ctrl.done
uart/VHDLoo/uart_ctrl/uart_ctrl.fit.eqn
uart/VHDLoo/uart_ctrl/uart_ctrl.fit.rpt
uart/VHDLoo/uart_ctrl/uart_ctrl.fit.summary
uart/VHDLoo/uart_ctrl/uart_ctrl.flow.rpt
uart/VHDLoo/uart_ctrl/uart_ctrl.map.eqn
uart/VHDLoo/uart_ctrl/uart_ctrl.map.rpt
uart/VHDLoo/uart_ctrl/uart_ctrl.map.summary
uart/VHDLoo/uart_ctrl/uart_ctrl.pin
uart/VHDLoo/uart_ctrl/uart_ctrl.pof
uart/VHDLoo/uart_ctrl/uart_ctrl.qpf
uart/VHDLoo/uart_ctrl/uart_ctrl.qsf
uart/VHDLoo/uart_ctrl/uart_ctrl.qws
uart/VHDLoo/uart_ctrl
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