文件名称:signal_cpu_sort
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- 上传时间：2008-10-13
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文件大小：8.75kb
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Use the verilog language write a MIPS CPU code, and have additional instruction, for example: selection sort instruction.
The code has contain combination circuit and sequenial circuit.
CPU have contain ALU, ADD, ALU_CONTROL, DATA_MEMORY, INST_MEMORY, REGISTER, PC, and TESTBRANCH.-Use the verilog language write a MIPS CPU code, and have additional instruction, for example: selection sort instruction. The code has contain combination circuit and sequenial circuit. CPU have contain ALU, ADD, ALU_CONTROL, DATA_MEMORY, INST_MEMORY, REGISTER, PC, and TESTBRANCH.
The code has contain combination circuit and sequenial circuit.
CPU have contain ALU, ADD, ALU_CONTROL, DATA_MEMORY, INST_MEMORY, REGISTER, PC, and TESTBRANCH.-Use the verilog language write a MIPS CPU code, and have additional instruction, for example: selection sort instruction. The code has contain combination circuit and sequenial circuit. CPU have contain ALU, ADD, ALU_CONTROL, DATA_MEMORY, INST_MEMORY, REGISTER, PC, and TESTBRANCH.
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下载文件列表
signal_cpu_sort/Add.v
signal_cpu_sort/Alu.v
signal_cpu_sort/Alu_control.v
signal_cpu_sort/Control.v
signal_cpu_sort/Data_memory.v
signal_cpu_sort/Instruction_memory.v
signal_cpu_sort/Line_control.v
signal_cpu_sort/Pc.v
signal_cpu_sort/Registers.v
signal_cpu_sort/Sign_extend.v
signal_cpu_sort/Single_cycle_cpu.v
signal_cpu_sort/test.prj
signal_cpu_sort/test.v
signal_cpu_sort/testbranch.v
signal_cpu_sort
www.dssz.com.txt
signal_cpu_sort/Alu.v
signal_cpu_sort/Alu_control.v
signal_cpu_sort/Control.v
signal_cpu_sort/Data_memory.v
signal_cpu_sort/Instruction_memory.v
signal_cpu_sort/Line_control.v
signal_cpu_sort/Pc.v
signal_cpu_sort/Registers.v
signal_cpu_sort/Sign_extend.v
signal_cpu_sort/Single_cycle_cpu.v
signal_cpu_sort/test.prj
signal_cpu_sort/test.v
signal_cpu_sort/testbranch.v
signal_cpu_sort
www.dssz.com.txt
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