eco_tutorial/
eco_tutorial/.synopsys_dc.setup
eco_tutorial/db/
eco_tutorial/db/eco_implemented.db
eco_tutorial/db/eco_optimized.db
eco_tutorial/db/eco_recycled.db
eco_tutorial/db/new_hdl.db
eco_tutorial/db/new_netlist.db
eco_tutorial/db/old_hdl.db
eco_tutorial/db/old_netlist.db
eco_tutorial/db/old_net_u.db
eco_tutorial/README
eco_tutorial/reports/
eco_tutorial/scripts/
eco_tutorial/scripts/create_db.scr
eco_tutorial/scripts/eco.script
eco_tutorial/scripts/spare_cell
eco_tutorial/scripts/uwave_ctl.pdef
eco_tutorial/src/
eco_tutorial/src/nu_uwave.v
eco_tutorial/src/nu_uwave.vhd
eco_tutorial/src/uwave.v
eco_tutorial/src/uwave.vhd
eco_tutorial/work/
examples/
examples/bc_view/
examples/bc_view/verilog/
examples/bc_view/verilog/.synopsys_dc.setup
examples/bc_view/verilog/db/
examples/bc_view/verilog/db/example.db
examples/bc_view/verilog/example.proj
examples/bc_view/verilog/hdl/
examples/bc_view/verilog/hdl/example.v
examples/bc_view/verilog/hdl/mult_proc.v
examples/bc_view/verilog/mult_proc.scr
examples/bc_view/verilog/rams/
examples/bc_view/verilog/rams/cs_rams.sl
examples/bc_view/verilog/rams/cs_rams.sldb
examples/bc_view/verilog/reports/
examples/bc_view/verilog/reports/example.rpt
examples/bc_view/verilog/scr/
examples/bc_view/verilog/scr/example.scr
examples/bc_view/verilog/soln/
examples/bc_view/verilog/soln/mult_proc.v
examples/bc_view/verilog/work/
examples/bc_view/verilog/work/example%verilog.syn
examples/bc_view/verilog/work/example%verilog__verilog.syn
examples/bc_view/verilog/work/EXAMPLE.mr
examples/bc_view/verilog/work/example.v.bi
examples/bc_view/verilog/work/example.v.id
examples/bc_view/vhdl/
examples/bc_view/vhdl/.synopsys_dc.setup
examples/bc_view/vhdl/db/
examples/bc_view/vhdl/db/example.db
examples/bc_view/vhdl/example.proj
examples/bc_view/vhdl/hdl/
examples/bc_view/vhdl/hdl/example.vhd
examples/bc_view/vhdl/hdl/mult_proc.vhd
examples/bc_view/vhdl/mult_proc.scr
examples/bc_view/vhdl/rams/
examples/bc_view/vhdl/rams/cs_rams.sl
examples/bc_view/vhdl/rams/cs_rams.sldb
examples/bc_view/vhdl/reports/
examples/bc_view/vhdl/reports/example.rpt
examples/bc_view/vhdl/scr/
examples/bc_view/vhdl/scr/example.scr
examples/bc_view/vhdl/soln/
examples/bc_view/vhdl/soln/mult_proc.vhd
examples/bc_view/vhdl/work/
examples/bc_view/vhdl/work/EXAMPLE.mr
examples/bc_view/vhdl/work/EXAMPLE.st
examples/bc_view/vhdl/work/EXAMPLE.syn
examples/bc_view/vhdl/work/example.vhd.bi
examples/bc_view/vhdl/work/example.vhd.id
examples/bc_view/vhdl/work/EXAMPLE__BEHAVIORAL.st
examples/bc_view/vhdl/work/EXAMPLE__BEHAVIORAL.syn
examples/dotfiles/
examples/dotfiles/cshrc
examples/dotfiles/nm_rules.dcsh
examples/dotfiles/synopsys
examples/dotfiles/Xdefaults
examples/fsm/
examples/fsm/.synopsys_dc.setup
examples/fsm/proc2.db
examples/fsm/proc2.v
examples/fsm/proc2.vhd
examples/fsm/proc3.db
examples/fsm/proc3.v
examples/fsm/proc3.vhd
examples/fsm/proc4.db
examples/fsm/proc4.v
examples/fsm/proc4.vhd
examples/fsm/work/
examples/README
examples/rtl_analyzer/
examples/rtl_analyzer/verilog/
examples/rtl_analyzer/verilog/.synopsys_dc.setup
examples/rtl_analyzer/verilog/clean
examples/rtl_analyzer/verilog/gtech/
examples/rtl_analyzer/verilog/gtech/addr_combo.ra
examples/rtl_analyzer/verilog/gtech/addr_combo.v.bi
examples/rtl_analyzer/verilog/gtech/addr_combo.v.id
examples/rtl_analyzer/verilog/gtech/addr_fsm.ra
examples/rtl_analyzer/verilog/gtech/addr_fsm.v.bi
examples/rtl_analyzer/verilog/gtech/addr_fsm.v.id
examples/rtl_analyzer/verilog/gtech/top.ra
examples/rtl_analyzer/verilog/gtech/top.v.bi
examples/rtl_analyzer/verilog/gtech/top.v.id
examples/rtl_analyzer/verilog/gtech_fast/
examples/rtl_analyzer/verilog/hdl/
examples/rtl_analyzer/verilog/hdl/addr_combo.v
examples/rtl_analyzer/verilog/hdl/addr_combo_fast.v
examples/rtl_analyzer/verilog/hdl/addr_fsm.v
examples/rtl_analyzer/verilog/hdl/top.v
examples/rtl_analyzer/verilog/libs/
examples/rtl_analyzer/verilog/libs/class.db
examples/rtl_analyzer/verilog/mapped/
examples/rtl_analyzer/verilog/mapped/top_mapped.db
examples/rtl_analyzer/verilog/projs/
examples/rtl_analyzer/verilog/projs/top_cons.scr
examples/rtl_analyzer/verilog/projs/top_gtech.proj
examples/rtl_analyzer/verilog/projs/top_mapped.proj
examples/rtl_analyzer/verilog/reports/
examples/rtl_analyzer/verilog/reports/top_area.rpt
examples/rtl_analyzer/verilog/reports/top_gtech_chk.rpt
examples/rtl_analyzer/verilog/reports/top_mapped_chk.rpt
examples/rtl_analyzer/verilog/reports/top_timing.rpt
examples/rtl_analyzer/verilog/scripts/
examples/rtl_analyzer/verilog/scripts/constraints.scr
examples/rtl_analyzer/verilog/scripts/gtech.scr
examples/rtl_analyzer/verilog/scripts/gtech_fast.scr
examples/rtl_analyzer/verilog/scripts/mapped.scr
examples/rtl_analyzer/verilog/scripts/mapped_fast.scr
examples/rtl_analyzer/verilog/scripts/recompile.scr
examples/rtl_analyzer/verilog/scripts/setup.scr
examples/rtl_analyzer/verilog/scripts/setup_fast.scr
examples/rtl_analyzer/verilog/scripts/top.scr
examples/rtl_analyzer/verilog/scripts/top_const.scr
examples/rtl_analyzer/verilog/scripts/top_fast.scr
examples/rtl_analyzer/verilog/unmapped/
examples/rtl_analyzer/verilog/u