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文件名称:m1_xsi_hdl

  • 所属分类：
    VHDL编程
  • 标签属性：
    [VHDL] [源码]
  • 上传时间：
    2008-10-13
  • 文件大小：
    7.5mb
  • 已下载：
    0次
  • 提 供 者：
    人***
  • 相关连接：
    无
  • 下载说明：
    别用迅雷下载，失败请重下，重下不扣分！
修正介绍说明

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实用的程序代码，希望对大家有用，已经调试通过
(系统自动生成,下载前可以参看下载内容)

下载文件列表

5k_preset/
5k_preset/VHDL/
5k_preset/VHDL/preset_5k.log
5k_preset/VHDL/WORK/
5k_preset/VHDL/WORK/PRESET_5K.sim
5k_preset/VHDL/WORK/PRESET_5K__BEHAV.sim
5k_preset/VHDL/WORK/PRESET_5K.mra
5k_preset/VHDL/WORK/PRESET_5K.syn
5k_preset/VHDL/WORK/PRESET_5K__BEHAV.syn
5k_preset/VHDL/.synopsys_dc.setup
5k_preset/VHDL/command.log
5k_preset/VHDL/M1_files/
5k_preset/VHDL/M1_files/preset_5k.sxnf
5k_preset/VHDL/M1_files/preset_5k.ncf
5k_preset/VHDL/M1_files/command.his
5k_preset/VHDL/M1_files/ngdbuild.log
5k_preset/VHDL/M1_files/netlist.lst
5k_preset/VHDL/M1_files/preset_5k.ngo
5k_preset/VHDL/M1_files/preset_5k.ngd
5k_preset/VHDL/M1_files/preset_5k.bld
5k_preset/VHDL/M1_files/map.mrp
5k_preset/VHDL/M1_files/map.ngm
5k_preset/VHDL/M1_files/preset_5k.pcf
5k_preset/VHDL/M1_files/map.ncd
5k_preset/VHDL/M1_files/map.pcf
5k_preset/VHDL/M1_files/preset_5k.par
5k_preset/VHDL/M1_files/preset_5k.ncd
5k_preset/VHDL/M1_files/preset_5k.dly
5k_preset/VHDL/M1_files/preset_5k.pad
5k_preset/VHDL/M1_files/preset_5k.twr
5k_preset/VHDL/M1_files/time_sim.alf
5k_preset/VHDL/M1_files/time_sim.nga
5k_preset/VHDL/M1_files/time_sim.vhd
5k_preset/VHDL/M1_files/time_sim.sdf
5k_preset/VHDL/M1_files/preset_5k.bgn
5k_preset/VHDL/M1_files/preset_5k.drc
5k_preset/VHDL/M1_files/preset_5k.bit
5k_preset/VHDL/preset_5k.vhd
5k_preset/VHDL/preset_5k.script
5k_preset/VHDL/preset_5k.fpga
5k_preset/VHDL/preset_5k.timing
5k_preset/VHDL/preset_5k.sxnf
5k_preset/VHDL/preset_5k.db
5k_preset/VHDL/preset_5k.ncf
5k_preset/VHDL/dc2ncf.log
5k_preset/VHDL/preset_5k.dc
5k_preset/Verilog/
5k_preset/Verilog/preset_5k.v
5k_preset/Verilog/preset_5k.log
5k_preset/Verilog/.synopsys_dc.setup
5k_preset/Verilog/M1_files/
5k_preset/Verilog/M1_files/preset_5k.sxnf
5k_preset/Verilog/M1_files/preset_5k.ncf
5k_preset/Verilog/M1_files/command.his
5k_preset/Verilog/M1_files/ngdbuild.log
5k_preset/Verilog/M1_files/netlist.lst
5k_preset/Verilog/M1_files/preset_5k.ngo
5k_preset/Verilog/M1_files/preset_5k.ngd
5k_preset/Verilog/M1_files/preset_5k.bld
5k_preset/Verilog/M1_files/map.mrp
5k_preset/Verilog/M1_files/map.ngm
5k_preset/Verilog/M1_files/preset_5k.pcf
5k_preset/Verilog/M1_files/map.ncd
5k_preset/Verilog/M1_files/map.pcf
5k_preset/Verilog/M1_files/preset_5k.par
5k_preset/Verilog/M1_files/preset_5k.ncd
5k_preset/Verilog/M1_files/preset_5k.dly
5k_preset/Verilog/M1_files/preset_5k.pad
5k_preset/Verilog/M1_files/preset_5k.twr
5k_preset/Verilog/M1_files/time_sim.alf
5k_preset/Verilog/M1_files/time_sim.nga
5k_preset/Verilog/M1_files/time_sim.v
5k_preset/Verilog/M1_files/time_sim.sdf
5k_preset/Verilog/M1_files/time_sim.tv
5k_preset/Verilog/M1_files/time_sim.pin
5k_preset/Verilog/M1_files/preset_5k.bgn
5k_preset/Verilog/M1_files/preset_5k.drc
5k_preset/Verilog/M1_files/preset_5k.bit
5k_preset/Verilog/preset_5k.script
5k_preset/Verilog/command.log
5k_preset/Verilog/preset_5k.fpga
5k_preset/Verilog/preset_5k.timing
5k_preset/Verilog/preset_5k.sxnf
5k_preset/Verilog/preset_5k.db
5k_preset/Verilog/preset_5k.ncf
5k_preset/Verilog/dc2ncf.log
5k_preset/Verilog/preset_5k.dc
Barrel_SR/
Barrel_SR/VHDL/
Barrel_SR/VHDL/Barrel_Org/
Barrel_SR/VHDL/Barrel_Org/WORK/
Barrel_SR/VHDL/Barrel_Org/WORK/BARREL_ORG.sim
Barrel_SR/VHDL/Barrel_Org/WORK/BARREL_ORG__RTL.sim
Barrel_SR/VHDL/Barrel_Org/WORK/BARREL_ORG.mra
Barrel_SR/VHDL/Barrel_Org/WORK/BARREL_ORG.syn
Barrel_SR/VHDL/Barrel_Org/WORK/BARREL_ORG__RTL.syn
Barrel_SR/VHDL/Barrel_Org/barrel_org.script
Barrel_SR/VHDL/Barrel_Org/barrel_org.vhd
Barrel_SR/VHDL/Barrel_Org/command.log
Barrel_SR/VHDL/Barrel_Org/.synopsys_dc.setup
Barrel_SR/VHDL/Barrel_Org/M1_files/
Barrel_SR/VHDL/Barrel_Org/M1_files/barrel_org.sxnf
Barrel_SR/VHDL/Barrel_Org/M1_files/barrel_org.ncf
Barrel_SR/VHDL/Barrel_Org/M1_files/command.his
Barrel_SR/VHDL/Barrel_Org/M1_files/ngdbuild.log
Barrel_SR/VHDL/Barrel_Org/M1_files/netlist.lst
Barrel_SR/VHDL/Barrel_Org/M1_files/barrel_org.ngo
Barrel_SR/VHDL/Barrel_Org/M1_files/barrel_org.ngd
Barrel_SR/VHDL/Barrel_Org/M1_files/barrel_org.bld
Barrel_SR/VHDL/Barrel_Org/M1_files/map.mrp
Barrel_SR/VHDL/Barrel_Org/M1_files/map.ngm
Barrel_SR/VHDL/Barrel_Org/M1_files/barrel_org.pcf
Barrel_SR/VHDL/Barrel_Org/M1_files/map.ncd
Barrel_SR/VHDL/Barrel_Org/M1_files/map.pcf
Barrel_SR/VHDL/Barrel_Org/M1_files/barrel_org.par
Barrel_SR/VHDL/Barrel_Org/M1_files/barrel_org.ncd
Barrel_SR/VHDL/Barrel_Org/M1_files/barrel_org.dly
Barrel_SR/VHDL/Barrel_Org/M1_files/barrel_org.pad
Barrel_SR/VHDL/Barrel_Org/M1_files/barrel_org.twr
Barrel_SR/VHDL/Barrel_Org/M1_files/time_sim.alf
Barrel_SR/VHDL/Barrel_Org/M1_files/time_sim.nga
Barrel_SR/VHDL/Barrel_Org/M1_files/time_sim.vhd
Barrel_SR/VHDL/Barrel_Org/M1_files/time_sim.sdf
Barrel_SR/VHDL/Barrel_Org/M1_files/barrel_org.bgn
Barrel_SR/VHDL/Barrel_Org/M1_files/barrel_org.drc
Barrel_SR/VHDL/Barrel_Org/M1_files/barrel_org.bit
Barrel_SR/VHDL/Barrel_Org/barrel_org.log
Barrel_SR/VHDL/Barrel_Org/barrel_org.fpga
Barrel_SR/VHDL/Barrel_Org/barrel_org.timing
Barrel_SR/VHDL/Barrel_Org/barrel_org.sxnf
Barrel_SR/VHDL/Barrel_Org/barrel_org.db
Barrel_SR/VHDL/Barrel_Org/barrel_org.ncf
Barrel_SR/VHDL/Barrel_Org/dc2ncf.log
Barrel_SR/VHDL/Barrel_Org/barrel_org.dc
Barrel_SR/VHDL/.synops

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