文件名称:an499_design_example
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cpld 控制 8-32M sdram 控制器 maxII epm570实现。
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下载文件列表
an499_design_example/Mobile_DRAM_Altera_MAX_II_CPLD_Design_Example/code/addr_gen.v
an499_design_example/Mobile_DRAM_Altera_MAX_II_CPLD_Design_Example/code/mobile_sdram.v
an499_design_example/Mobile_DRAM_Altera_MAX_II_CPLD_Design_Example/code/upcount_2.v
an499_design_example/Mobile_DRAM_Altera_MAX_II_CPLD_Design_Example/code/upcount_4.v
an499_design_example/Mobile_DRAM_Altera_MAX_II_CPLD_Design_Example/code
an499_design_example/Mobile_DRAM_Altera_MAX_II_CPLD_Design_Example/modelsim/addr_gen.v
an499_design_example/Mobile_DRAM_Altera_MAX_II_CPLD_Design_Example/modelsim/mobile_sdram.cr.mti
an499_design_example/Mobile_DRAM_Altera_MAX_II_CPLD_Design_Example/modelsim/mobile_sdram.mpf
an499_design_example/Mobile_DRAM_Altera_MAX_II_CPLD_Design_Example/modelsim/mobile_sdram.v
an499_design_example/Mobile_DRAM_Altera_MAX_II_CPLD_Design_Example/modelsim/test_mob_sdram.v
an499_design_example/Mobile_DRAM_Altera_MAX_II_CPLD_Design_Example/modelsim/upcount_2.v
an499_design_example/Mobile_DRAM_Altera_MAX_II_CPLD_Design_Example/modelsim/upcount_4.v
an499_design_example/Mobile_DRAM_Altera_MAX_II_CPLD_Design_Example/modelsim/vsim.wlf
an499_design_example/Mobile_DRAM_Altera_MAX_II_CPLD_Design_Example/modelsim/wave.bmp
an499_design_example/Mobile_DRAM_Altera_MAX_II_CPLD_Design_Example/modelsim/wave.do
an499_design_example/Mobile_DRAM_Altera_MAX_II_CPLD_Design_Example/modelsim/work/addr_gen/verilog.psm
an499_design_example/Mobile_DRAM_Altera_MAX_II_CPLD_Design_Example/modelsim/work/addr_gen/_primary.dat
an499_design_example/Mobile_DRAM_Altera_MAX_II_CPLD_Design_Example/modelsim/work/addr_gen/_primary.vhd
an499_design_example/Mobile_DRAM_Altera_MAX_II_CPLD_Design_Example/modelsim/work/addr_gen
an499_design_example/Mobile_DRAM_Altera_MAX_II_CPLD_Design_Example/modelsim/work/mobile_sdram/verilog.psm
an499_design_example/Mobile_DRAM_Altera_MAX_II_CPLD_Design_Example/modelsim/work/mobile_sdram/_primary.dat
an499_design_example/Mobile_DRAM_Altera_MAX_II_CPLD_Design_Example/modelsim/work/mobile_sdram/_primary.vhd
an499_design_example/Mobile_DRAM_Altera_MAX_II_CPLD_Design_Example/modelsim/work/mobile_sdram
an499_design_example/Mobile_DRAM_Altera_MAX_II_CPLD_Design_Example/modelsim/work/test_mob_sdram/verilog.psm
an499_design_example/Mobile_DRAM_Altera_MAX_II_CPLD_Design_Example/modelsim/work/test_mob_sdram/_primary.dat
an499_design_example/Mobile_DRAM_Altera_MAX_II_CPLD_Design_Example/modelsim/work/test_mob_sdram/_primary.vhd
an499_design_example/Mobile_DRAM_Altera_MAX_II_CPLD_Design_Example/modelsim/work/test_mob_sdram
an499_design_example/Mobile_DRAM_Altera_MAX_II_CPLD_Design_Example/modelsim/work/upcount_2/verilog.psm
an499_design_example/Mobile_DRAM_Altera_MAX_II_CPLD_Design_Example/modelsim/work/upcount_2/_primary.dat
an499_design_example/Mobile_DRAM_Altera_MAX_II_CPLD_Design_Example/modelsim/work/upcount_2/_primary.vhd
an499_design_example/Mobile_DRAM_Altera_MAX_II_CPLD_Design_Example/modelsim/work/upcount_2
an499_design_example/Mobile_DRAM_Altera_MAX_II_CPLD_Design_Example/modelsim/work/upcount_4/verilog.psm
an499_design_example/Mobile_DRAM_Altera_MAX_II_CPLD_Design_Example/modelsim/work/upcount_4/_primary.dat
an499_design_example/Mobile_DRAM_Altera_MAX_II_CPLD_Design_Example/modelsim/work/upcount_4/_primary.vhd
an499_design_example/Mobile_DRAM_Altera_MAX_II_CPLD_Design_Example/modelsim/work/upcount_4
an499_design_example/Mobile_DRAM_Altera_MAX_II_CPLD_Design_Example/modelsim/work/_info
an499_design_example/Mobile_DRAM_Altera_MAX_II_CPLD_Design_Example/modelsim/work
an499_design_example/Mobile_DRAM_Altera_MAX_II_CPLD_Design_Example/modelsim
an499_design_example/Mobile_DRAM_Altera_MAX_II_CPLD_Design_Example/quartus/addr_gen.v
an499_design_example/Mobile_DRAM_Altera_MAX_II_CPLD_Design_Example/quartus/db/mobile_sdram.(0).cnf.cdb
an499_design_example/Mobile_DRAM_Altera_MAX_II_CPLD_Design_Example/quartus/db/mobile_sdram.(0).cnf.hdb
an499_design_example/Mobile_DRAM_Altera_MAX_II_CPLD_Design_Example/quartus/db/mobile_sdram.(1).cnf.cdb
an499_design_example/Mobile_DRAM_Altera_MAX_II_CPLD_Design_Example/quartus/db/mobile_sdram.(1).cnf.hdb
an499_design_example/Mobile_DRAM_Altera_MAX_II_CPLD_Design_Example/quartus/db/mobile_sdram.(2).cnf.cdb
an499_design_example/Mobile_DRAM_Altera_MAX_II_CPLD_Design_Example/quartus/db/mobile_sdram.(2).cnf.hdb
an499_design_example/Mobile_DRAM_Altera_MAX_II_CPLD_Design_Example/quartus/db/mobile_sdram.(3).cnf.cdb
an499_design_example/Mobile_DRAM_Altera_MAX_II_CPLD_Design_Example/quartus/db/mobile_sdram.(3).cnf.hdb
an499_design_example/Mobile_DRAM_Altera_MAX_II_CPLD_Design_Example/quartus/db/mobile_sdram.asm.qmsg
an499_design_example/Mobile_DRAM_Altera_MAX_II_CPLD_Design_Example/quartus/db/mobile_sdram.asm_labs.ddb
an499_design_example/Mobile_DRAM_Altera_MAX_II_CPLD_Design_Example/quartus/db/mobile_sdram.cbx.xml
an499_design_example/Mobile_DRAM_Altera_MAX_II_CPLD_Design_Example/quartus/db/mobile_sdram.cmp.cdb
an499_design_example/Mobile_DRAM_Altera_MAX_II_CPLD_Design_Example/quartus/db/mobile_sdram.cmp.hdb
an499_design_example/Mobile_DRAM_Altera_MAX_II_CPLD_Design_Example/quartus/db/mobile_sdram.cmp.kpt
an499_design_example/Mobile_
an499_design_example/Mobile_DRAM_Altera_MAX_II_CPLD_Design_Example/code/mobile_sdram.v
an499_design_example/Mobile_DRAM_Altera_MAX_II_CPLD_Design_Example/code/upcount_2.v
an499_design_example/Mobile_DRAM_Altera_MAX_II_CPLD_Design_Example/code/upcount_4.v
an499_design_example/Mobile_DRAM_Altera_MAX_II_CPLD_Design_Example/code
an499_design_example/Mobile_DRAM_Altera_MAX_II_CPLD_Design_Example/modelsim/addr_gen.v
an499_design_example/Mobile_DRAM_Altera_MAX_II_CPLD_Design_Example/modelsim/mobile_sdram.cr.mti
an499_design_example/Mobile_DRAM_Altera_MAX_II_CPLD_Design_Example/modelsim/mobile_sdram.mpf
an499_design_example/Mobile_DRAM_Altera_MAX_II_CPLD_Design_Example/modelsim/mobile_sdram.v
an499_design_example/Mobile_DRAM_Altera_MAX_II_CPLD_Design_Example/modelsim/test_mob_sdram.v
an499_design_example/Mobile_DRAM_Altera_MAX_II_CPLD_Design_Example/modelsim/upcount_2.v
an499_design_example/Mobile_DRAM_Altera_MAX_II_CPLD_Design_Example/modelsim/upcount_4.v
an499_design_example/Mobile_DRAM_Altera_MAX_II_CPLD_Design_Example/modelsim/vsim.wlf
an499_design_example/Mobile_DRAM_Altera_MAX_II_CPLD_Design_Example/modelsim/wave.bmp
an499_design_example/Mobile_DRAM_Altera_MAX_II_CPLD_Design_Example/modelsim/wave.do
an499_design_example/Mobile_DRAM_Altera_MAX_II_CPLD_Design_Example/modelsim/work/addr_gen/verilog.psm
an499_design_example/Mobile_DRAM_Altera_MAX_II_CPLD_Design_Example/modelsim/work/addr_gen/_primary.dat
an499_design_example/Mobile_DRAM_Altera_MAX_II_CPLD_Design_Example/modelsim/work/addr_gen/_primary.vhd
an499_design_example/Mobile_DRAM_Altera_MAX_II_CPLD_Design_Example/modelsim/work/addr_gen
an499_design_example/Mobile_DRAM_Altera_MAX_II_CPLD_Design_Example/modelsim/work/mobile_sdram/verilog.psm
an499_design_example/Mobile_DRAM_Altera_MAX_II_CPLD_Design_Example/modelsim/work/mobile_sdram/_primary.dat
an499_design_example/Mobile_DRAM_Altera_MAX_II_CPLD_Design_Example/modelsim/work/mobile_sdram/_primary.vhd
an499_design_example/Mobile_DRAM_Altera_MAX_II_CPLD_Design_Example/modelsim/work/mobile_sdram
an499_design_example/Mobile_DRAM_Altera_MAX_II_CPLD_Design_Example/modelsim/work/test_mob_sdram/verilog.psm
an499_design_example/Mobile_DRAM_Altera_MAX_II_CPLD_Design_Example/modelsim/work/test_mob_sdram/_primary.dat
an499_design_example/Mobile_DRAM_Altera_MAX_II_CPLD_Design_Example/modelsim/work/test_mob_sdram/_primary.vhd
an499_design_example/Mobile_DRAM_Altera_MAX_II_CPLD_Design_Example/modelsim/work/test_mob_sdram
an499_design_example/Mobile_DRAM_Altera_MAX_II_CPLD_Design_Example/modelsim/work/upcount_2/verilog.psm
an499_design_example/Mobile_DRAM_Altera_MAX_II_CPLD_Design_Example/modelsim/work/upcount_2/_primary.dat
an499_design_example/Mobile_DRAM_Altera_MAX_II_CPLD_Design_Example/modelsim/work/upcount_2/_primary.vhd
an499_design_example/Mobile_DRAM_Altera_MAX_II_CPLD_Design_Example/modelsim/work/upcount_2
an499_design_example/Mobile_DRAM_Altera_MAX_II_CPLD_Design_Example/modelsim/work/upcount_4/verilog.psm
an499_design_example/Mobile_DRAM_Altera_MAX_II_CPLD_Design_Example/modelsim/work/upcount_4/_primary.dat
an499_design_example/Mobile_DRAM_Altera_MAX_II_CPLD_Design_Example/modelsim/work/upcount_4/_primary.vhd
an499_design_example/Mobile_DRAM_Altera_MAX_II_CPLD_Design_Example/modelsim/work/upcount_4
an499_design_example/Mobile_DRAM_Altera_MAX_II_CPLD_Design_Example/modelsim/work/_info
an499_design_example/Mobile_DRAM_Altera_MAX_II_CPLD_Design_Example/modelsim/work
an499_design_example/Mobile_DRAM_Altera_MAX_II_CPLD_Design_Example/modelsim
an499_design_example/Mobile_DRAM_Altera_MAX_II_CPLD_Design_Example/quartus/addr_gen.v
an499_design_example/Mobile_DRAM_Altera_MAX_II_CPLD_Design_Example/quartus/db/mobile_sdram.(0).cnf.cdb
an499_design_example/Mobile_DRAM_Altera_MAX_II_CPLD_Design_Example/quartus/db/mobile_sdram.(0).cnf.hdb
an499_design_example/Mobile_DRAM_Altera_MAX_II_CPLD_Design_Example/quartus/db/mobile_sdram.(1).cnf.cdb
an499_design_example/Mobile_DRAM_Altera_MAX_II_CPLD_Design_Example/quartus/db/mobile_sdram.(1).cnf.hdb
an499_design_example/Mobile_DRAM_Altera_MAX_II_CPLD_Design_Example/quartus/db/mobile_sdram.(2).cnf.cdb
an499_design_example/Mobile_DRAM_Altera_MAX_II_CPLD_Design_Example/quartus/db/mobile_sdram.(2).cnf.hdb
an499_design_example/Mobile_DRAM_Altera_MAX_II_CPLD_Design_Example/quartus/db/mobile_sdram.(3).cnf.cdb
an499_design_example/Mobile_DRAM_Altera_MAX_II_CPLD_Design_Example/quartus/db/mobile_sdram.(3).cnf.hdb
an499_design_example/Mobile_DRAM_Altera_MAX_II_CPLD_Design_Example/quartus/db/mobile_sdram.asm.qmsg
an499_design_example/Mobile_DRAM_Altera_MAX_II_CPLD_Design_Example/quartus/db/mobile_sdram.asm_labs.ddb
an499_design_example/Mobile_DRAM_Altera_MAX_II_CPLD_Design_Example/quartus/db/mobile_sdram.cbx.xml
an499_design_example/Mobile_DRAM_Altera_MAX_II_CPLD_Design_Example/quartus/db/mobile_sdram.cmp.cdb
an499_design_example/Mobile_DRAM_Altera_MAX_II_CPLD_Design_Example/quartus/db/mobile_sdram.cmp.hdb
an499_design_example/Mobile_DRAM_Altera_MAX_II_CPLD_Design_Example/quartus/db/mobile_sdram.cmp.kpt
an499_design_example/Mobile_
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