文件名称:PWM
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脉冲宽度调制,VHDL代码编写,包括QUARTUSII和MODELSIM工程以及testbench
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下载文件列表
脉冲宽度调制/an501.pdf
脉冲宽度调制/AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example/code/pwm_main.v
脉冲宽度调制/AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example/modelsim/pulse_width_modulator.cr.mti
脉冲宽度调制/AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example/modelsim/pulse_width_modulator.mpf
脉冲宽度调制/AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example/modelsim/pwm_main.v
脉冲宽度调制/AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example/modelsim/pwm_sim.cr.mti
脉冲宽度调制/AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example/modelsim/pwm_sim.mpf
脉冲宽度调制/AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example/modelsim/test_pwm.v
脉冲宽度调制/AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example/modelsim/wave.bmp
脉冲宽度调制/AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example/modelsim/wave.do
脉冲宽度调制/AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example/modelsim/wave2.bmp
脉冲宽度调制/AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example/modelsim/wave2.do
脉冲宽度调制/AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example/modelsim/wave3.bmp
脉冲宽度调制/AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example/modelsim/wave3.do
脉冲宽度调制/AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example/modelsim/wave4.bmp
脉冲宽度调制/AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example/modelsim/wave4.do
脉冲宽度调制/AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example/modelsim/wave5.bmp
脉冲宽度调制/AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example/modelsim/wave5.do
脉冲宽度调制/AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example/modelsim/work/altufm_osc0_altufm_osc_1p3/verilog.asm
脉冲宽度调制/AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example/modelsim/work/altufm_osc0_altufm_osc_1p3/_primary.dat
脉冲宽度调制/AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example/modelsim/work/altufm_osc0_altufm_osc_1p3/_primary.vhd
脉冲宽度调制/AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example/modelsim/work/clkgen/verilog.asm
脉冲宽度调制/AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example/modelsim/work/clkgen/_primary.dat
脉冲宽度调制/AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example/modelsim/work/clkgen/_primary.vhd
脉冲宽度调制/AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example/modelsim/work/clk_gen/verilog.asm
脉冲宽度调制/AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example/modelsim/work/clk_gen/_primary.dat
脉冲宽度调制/AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example/modelsim/work/clk_gen/_primary.vhd
脉冲宽度调制/AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example/modelsim/work/dutycycle/verilog.asm
脉冲宽度调制/AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example/modelsim/work/dutycycle/_primary.dat
脉冲宽度调制/AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example/modelsim/work/dutycycle/_primary.vhd
脉冲宽度调制/AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example/modelsim/work/duty_cycle/verilog.asm
脉冲宽度调制/AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example/modelsim/work/duty_cycle/_primary.dat
脉冲宽度调制/AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example/modelsim/work/duty_cycle/_primary.vhd
脉冲宽度调制/AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example/modelsim/work/pwm_gen/verilog.asm
脉冲宽度调制/AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example/modelsim/work/pwm_gen/_primary.dat
脉冲宽度调制/AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example/modelsim/work/pwm_gen/_primary.vhd
脉冲宽度调制/AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example/modelsim/work/pwm_main/verilog.asm
脉冲宽度调制/AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example/modelsim/work/pwm_main/_primary.dat
脉冲宽度调制/AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example/modelsim/work/pwm_main/_primary.vhd
脉冲宽度调制/AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example/modelsim/work/test_pwm/verilog.asm
脉冲宽度调制/AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example/modelsim/work/test_pwm/_primary.dat
脉冲宽度调制/AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example/modelsim/work/test_pwm/_primary.vhd
脉冲宽度调制/AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example/modelsim/work/_info
脉冲宽度调制/AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example/quartus/db/pwm_main.(0).cnf.cdb
脉冲宽度调制/AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example/quartus/db/pwm_main.(0).cnf.hdb
脉冲宽度调制/AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example/quartus/db/pwm_main.(1).cnf.cdb
脉冲宽度调制/AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example/quartus/db/pwm_main.(1).cnf.hdb
脉冲宽度调制/AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example/quartus/db/pwm_main.(2).cnf.cdb
脉冲宽度调制/AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example/quartus/db/pwm_main.(2).cnf.hdb
脉冲宽度调制/AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example/quartus/db/pwm_main.(3).cnf.cdb
脉冲宽度调制/AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example/quartus/db/pwm_main.(3).cnf.hdb
脉冲宽度调制/AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example/quartus/db/pwm_main.(4).cnf.cdb
脉冲宽度调制/AN501
脉冲宽度调制/AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example/code/pwm_main.v
脉冲宽度调制/AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example/modelsim/pulse_width_modulator.cr.mti
脉冲宽度调制/AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example/modelsim/pulse_width_modulator.mpf
脉冲宽度调制/AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example/modelsim/pwm_main.v
脉冲宽度调制/AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example/modelsim/pwm_sim.cr.mti
脉冲宽度调制/AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example/modelsim/pwm_sim.mpf
脉冲宽度调制/AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example/modelsim/test_pwm.v
脉冲宽度调制/AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example/modelsim/wave.bmp
脉冲宽度调制/AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example/modelsim/wave.do
脉冲宽度调制/AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example/modelsim/wave2.bmp
脉冲宽度调制/AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example/modelsim/wave2.do
脉冲宽度调制/AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example/modelsim/wave3.bmp
脉冲宽度调制/AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example/modelsim/wave3.do
脉冲宽度调制/AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example/modelsim/wave4.bmp
脉冲宽度调制/AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example/modelsim/wave4.do
脉冲宽度调制/AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example/modelsim/wave5.bmp
脉冲宽度调制/AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example/modelsim/wave5.do
脉冲宽度调制/AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example/modelsim/work/altufm_osc0_altufm_osc_1p3/verilog.asm
脉冲宽度调制/AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example/modelsim/work/altufm_osc0_altufm_osc_1p3/_primary.dat
脉冲宽度调制/AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example/modelsim/work/altufm_osc0_altufm_osc_1p3/_primary.vhd
脉冲宽度调制/AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example/modelsim/work/clkgen/verilog.asm
脉冲宽度调制/AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example/modelsim/work/clkgen/_primary.dat
脉冲宽度调制/AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example/modelsim/work/clkgen/_primary.vhd
脉冲宽度调制/AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example/modelsim/work/clk_gen/verilog.asm
脉冲宽度调制/AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example/modelsim/work/clk_gen/_primary.dat
脉冲宽度调制/AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example/modelsim/work/clk_gen/_primary.vhd
脉冲宽度调制/AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example/modelsim/work/dutycycle/verilog.asm
脉冲宽度调制/AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example/modelsim/work/dutycycle/_primary.dat
脉冲宽度调制/AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example/modelsim/work/dutycycle/_primary.vhd
脉冲宽度调制/AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example/modelsim/work/duty_cycle/verilog.asm
脉冲宽度调制/AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example/modelsim/work/duty_cycle/_primary.dat
脉冲宽度调制/AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example/modelsim/work/duty_cycle/_primary.vhd
脉冲宽度调制/AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example/modelsim/work/pwm_gen/verilog.asm
脉冲宽度调制/AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example/modelsim/work/pwm_gen/_primary.dat
脉冲宽度调制/AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example/modelsim/work/pwm_gen/_primary.vhd
脉冲宽度调制/AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example/modelsim/work/pwm_main/verilog.asm
脉冲宽度调制/AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example/modelsim/work/pwm_main/_primary.dat
脉冲宽度调制/AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example/modelsim/work/pwm_main/_primary.vhd
脉冲宽度调制/AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example/modelsim/work/test_pwm/verilog.asm
脉冲宽度调制/AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example/modelsim/work/test_pwm/_primary.dat
脉冲宽度调制/AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example/modelsim/work/test_pwm/_primary.vhd
脉冲宽度调制/AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example/modelsim/work/_info
脉冲宽度调制/AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example/quartus/db/pwm_main.(0).cnf.cdb
脉冲宽度调制/AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example/quartus/db/pwm_main.(0).cnf.hdb
脉冲宽度调制/AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example/quartus/db/pwm_main.(1).cnf.cdb
脉冲宽度调制/AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example/quartus/db/pwm_main.(1).cnf.hdb
脉冲宽度调制/AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example/quartus/db/pwm_main.(2).cnf.cdb
脉冲宽度调制/AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example/quartus/db/pwm_main.(2).cnf.hdb
脉冲宽度调制/AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example/quartus/db/pwm_main.(3).cnf.cdb
脉冲宽度调制/AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example/quartus/db/pwm_main.(3).cnf.hdb
脉冲宽度调制/AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example/quartus/db/pwm_main.(4).cnf.cdb
脉冲宽度调制/AN501
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