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文件名称:usb1.1_Verilog

  • 所属分类：
    VHDL编程
  • 标签属性：
    [VHDL] [源码]
  • 上传时间：
    2008-10-13
  • 文件大小：
    128.66kb
  • 已下载：
    1次
  • 提 供 者：
    李***
  • 相关连接：
    无
  • 下载说明：
    别用迅雷下载，失败请重下，重下不扣分！
修正介绍说明

介绍说明－－下载内容来自于网络，使用问题请自行百度

usb1.1的设备控制器IP核，是用verilog硬件描述语言写的-USB1.1 IP core for device control, written with hardware describing language of Verilog.
(系统自动生成,下载前可以参看下载内容)

下载文件列表

usb1.1/test_bench/tests.v
usb1.1/test_bench/tests_lib.v
usb1.1/test_bench/db
usb1.1/test_bench/timescale.v
usb1.1/test_bench/test_bench_top.v
usb1.1/test_bench
usb1.1/generic_memories/generic_dpram.v
usb1.1/generic_memories
usb1.1/generic_fifos/generic_fifos.tar.gz
usb1.1/generic_fifos/generic_fifos/generic_fifos/sim/rtl_sim/run/waves/waves.do
usb1.1/generic_fifos/generic_fifos/generic_fifos/sim/rtl_sim/run/waves/CVS/Root
usb1.1/generic_fifos/generic_fifos/generic_fifos/sim/rtl_sim/run/waves/CVS/Repository
usb1.1/generic_fifos/generic_fifos/generic_fifos/sim/rtl_sim/run/waves/CVS/Entries
usb1.1/generic_fifos/generic_fifos/generic_fifos/sim/rtl_sim/run/waves/CVS
usb1.1/generic_fifos/generic_fifos/generic_fifos/sim/rtl_sim/run/waves
usb1.1/generic_fifos/generic_fifos/generic_fifos/sim/rtl_sim/run/CVS/Root
usb1.1/generic_fifos/generic_fifos/generic_fifos/sim/rtl_sim/run/CVS/Repository
usb1.1/generic_fifos/generic_fifos/generic_fifos/sim/rtl_sim/run/CVS/Entries
usb1.1/generic_fifos/generic_fifos/generic_fifos/sim/rtl_sim/run/CVS
usb1.1/generic_fifos/generic_fifos/generic_fifos/sim/rtl_sim/run
usb1.1/generic_fifos/generic_fifos/generic_fifos/sim/rtl_sim/bin/Makefile
usb1.1/generic_fifos/generic_fifos/generic_fifos/sim/rtl_sim/bin/CVS/Root
usb1.1/generic_fifos/generic_fifos/generic_fifos/sim/rtl_sim/bin/CVS/Repository
usb1.1/generic_fifos/generic_fifos/generic_fifos/sim/rtl_sim/bin/CVS/Entries
usb1.1/generic_fifos/generic_fifos/generic_fifos/sim/rtl_sim/bin/CVS
usb1.1/generic_fifos/generic_fifos/generic_fifos/sim/rtl_sim/bin
usb1.1/generic_fifos/generic_fifos/generic_fifos/sim/rtl_sim/CVS/Root
usb1.1/generic_fifos/generic_fifos/generic_fifos/sim/rtl_sim/CVS/Repository
usb1.1/generic_fifos/generic_fifos/generic_fifos/sim/rtl_sim/CVS/Entries
usb1.1/generic_fifos/generic_fifos/generic_fifos/sim/rtl_sim/CVS
usb1.1/generic_fifos/generic_fifos/generic_fifos/sim/rtl_sim
usb1.1/generic_fifos/generic_fifos/generic_fifos/sim/CVS/Root
usb1.1/generic_fifos/generic_fifos/generic_fifos/sim/CVS/Repository
usb1.1/generic_fifos/generic_fifos/generic_fifos/sim/CVS/Entries
usb1.1/generic_fifos/generic_fifos/generic_fifos/sim/CVS
usb1.1/generic_fifos/generic_fifos/generic_fifos/sim
usb1.1/generic_fifos/generic_fifos/generic_fifos/rtl/verilog/generic_fifo_dc.v
usb1.1/generic_fifos/generic_fifos/generic_fifos/rtl/verilog/generic_fifo_dc_gray.v
usb1.1/generic_fifos/generic_fifos/generic_fifos/rtl/verilog/generic_fifo_lfsr.v
usb1.1/generic_fifos/generic_fifos/generic_fifos/rtl/verilog/generic_fifo_sc_a.v
usb1.1/generic_fifos/generic_fifos/generic_fifos/rtl/verilog/generic_fifo_sc_b.v
usb1.1/generic_fifos/generic_fifos/generic_fifos/rtl/verilog/lfsr.v
usb1.1/generic_fifos/generic_fifos/generic_fifos/rtl/verilog/timescale.v
usb1.1/generic_fifos/generic_fifos/generic_fifos/rtl/verilog/CVS/Root
usb1.1/generic_fifos/generic_fifos/generic_fifos/rtl/verilog/CVS/Repository
usb1.1/generic_fifos/generic_fifos/generic_fifos/rtl/verilog/CVS/Entries
usb1.1/generic_fifos/generic_fifos/generic_fifos/rtl/verilog/CVS
usb1.1/generic_fifos/generic_fifos/generic_fifos/rtl/verilog
usb1.1/generic_fifos/generic_fifos/generic_fifos/rtl/CVS/Root
usb1.1/generic_fifos/generic_fifos/generic_fifos/rtl/CVS/Repository
usb1.1/generic_fifos/generic_fifos/generic_fifos/rtl/CVS/Entries
usb1.1/generic_fifos/generic_fifos/generic_fifos/rtl/CVS
usb1.1/generic_fifos/generic_fifos/generic_fifos/rtl
usb1.1/generic_fifos/generic_fifos/generic_fifos/doc/README.txt
usb1.1/generic_fifos/generic_fifos/generic_fifos/doc/CVS/Root
usb1.1/generic_fifos/generic_fifos/generic_fifos/doc/CVS/Repository
usb1.1/generic_fifos/generic_fifos/generic_fifos/doc/CVS/Entries
usb1.1/generic_fifos/generic_fifos/generic_fifos/doc/CVS
usb1.1/generic_fifos/generic_fifos/generic_fifos/doc
usb1.1/generic_fifos/generic_fifos/generic_fifos/bench/verilog/test_bench_top.v
usb1.1/generic_fifos/generic_fifos/generic_fifos/bench/verilog/CVS/Root
usb1.1/generic_fifos/generic_fifos/generic_fifos/bench/verilog/CVS/Repository
usb1.1/generic_fifos/generic_fifos/generic_fifos/bench/verilog/CVS/Entries
usb1.1/generic_fifos/generic_fifos/generic_fifos/bench/verilog/CVS
usb1.1/generic_fifos/generic_fifos/generic_fifos/bench/verilog
usb1.1/generic_fifos/generic_fifos/generic_fifos/bench/CVS/Root
usb1.1/generic_fifos/generic_fifos/generic_fifos/bench/CVS/Repository
usb1.1/generic_fifos/generic_fifos/generic_fifos/bench/CVS/Entries
usb1.1/generic_fifos/generic_fifos/generic_fifos/bench/CVS
usb1.1/generic_fifos/generic_fifos/generic_fifos/bench
usb1.1/generic_fifos/generic_fifos/generic_fifos/CVS/Root
usb1.1/generic_fifos/generic_fifos/generic_fifos/CVS/Repository
usb1.1/generic_fifos/generic_fifos/generic_fifos/CVS/Entries
usb1.1/generic_fifos/generic_fifos/generic_fifos/CVS
usb1.1/generic_fifos/generic_fifos/generic_fifos
usb1.1/generic_fifos/generic_fifos
usb1.1/generic_fifos
usb1.1/The USB 1.1 Function IP Core.txt
usb1.1/rtl/usb1_core.v
usb1.1/rtl/timescale.v
usb1.1/rtl/usb1_crc16.v
usb1.1/rtl/usb1_crc5.v
usb1.1/rtl/usb1_ctrl.v
usb1.1/rtl/usb1_fifo2.v
usb1.1/rtl/usb1_idma.v
usb1.1/rtl/usb1_pa.v
usb1.1/rtl/usb1_pd.v
usb1.1/rtl/usb1_pe.v
us

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