压缩包 : Verilog HDL程序设计教程之光盘资料 .rar 列表
readme.doc
source\chap10\acc.v
source\chap10\accn.v
source\chap10\add8.v
source\chap10\adder8.v
source\chap10\block1.v
source\chap10\block2.v
source\chap10\block3.v
source\chap10\block4.v
source\chap10\control.v
source\chap10\fsm.v
source\chap10\longframe1.v
source\chap10\longframe2.v
source\chap10\pipeline.v
source\chap10\reg8.v
source\chap10\resource1.v
source\chap10\resource2.v
source\chap11\account.v
source\chap11\clock.v
source\chap11\count10.v
source\chap11\fre_ctrl.v
source\chap11\latch_16.v
source\chap11\paobiao.v
source\chap11\sell.v
source\chap11\song.v
source\chap11\traffic.v
source\chap12\add_ahead.v
source\chap12\add_bx.v
source\chap12\add_jl.v
source\chap12\add_tree.v
source\chap12\correlator.v
source\chap12\crc.v
source\chap12\cycle.v
source\chap12\decoder1.v
source\chap12\decoder2.v
source\chap12\fir.v
source\chap12\linear.v
source\chap12\mult.v
source\chap12\mult4x4.v
source\chap3\adder4.v
source\chap3\adder_tp.v
source\chap3\aoi.v
source\chap3\count4.v
source\chap3\count4_tp.v
source\chap5\adder.v
source\chap5\adder16.v
source\chap5\alu.v
source\chap5\block.v
source\chap5\buried_ff.v
source\chap5\compile.v
source\chap5\count.v
source\chap5\count60.v
source\chap5\decode4_7.v
source\chap5\loop1.v
source\chap5\loop2.v
source\chap5\loop3.v
source\chap5\mult_for.v
source\chap5\mult_repeat.v
source\chap5\mux21_1.v
source\chap5\mux21_2.v
source\chap5\mux4_1.v
source\chap5\mux_casez.v
source\chap5\non_block.v
source\chap5\test.v
source\chap5\voter7.v
source\chap5\wave1.v
source\chap5\wave2.v
source\chap6\alutask.v
source\chap6\alu_tp.v
source\chap6\code_83.v
source\chap6\count.v
source\chap6\funct.v
source\chap6\funct_tp.v
source\chap6\paral1.v
source\chap6\paral2.v
source\chap6\serial1.v
source\chap6\serial2.v
source\chap7\add4_1.v
source\chap7\add4_2.v
source\chap7\add4_3.v
source\chap7\count4.v
source\chap7\full_add1.v
source\chap7\full_add2.v
source\chap7\full_add3.v
source\chap7\full_add4.v
source\chap7\full_add5.v
source\chap7\half_add1.v
source\chap7\half_add2.v
source\chap7\half_add3.v
source\chap7\half_add4.v
source\chap7\mux2_1a.v
source\chap7\mux2_1b.v
source\chap7\mux2_1c.v
source\chap7\mux4_1a.v
source\chap7\mux4_1b.v
source\chap7\mux4_1c.v
source\chap7\mux4_1d.v
source\chap8\add8_tp.v
source\chap8\carry_udp.v
source\chap8\carry_udpx1.v
source\chap8\carry_udpx2.v
source\chap8\count8_tp.v
source\chap8\delay.v
source\chap8\dff.v
source\chap8\dff_udp.v
source\chap8\latch.v
source\chap8\mult_tp.v
source\chap8\mux31.v
source\chap8\mux_tp.v
source\chap8\random_tp.v
source\chap8\rom.v
source\chap8\test1.v
source\chap8\test2.v
source\chap8\time_dif.v
source\chap9\bidir.v
source\chap9\bidir2.v
source\chap9\code_83.v
source\chap9\decode47.v
source\chap9\decoder_38.v
source\chap9\dff.v
source\chap9\dff1.v
source\chap9\dff2.v
source\chap9\encoder8_3.v
source\chap9\gate1.v
source\chap9\gate2.v
source\chap9\gate3.v
source\chap9\jk_ff.v
source\chap9\johnson.v
source\chap9\latch_1.v
source\chap9\latch_2.v
source\chap9\latch_8.v
source\chap9\mac.v
source\chap9\mac_tp.v
source\chap9\map_lpm_ram.v
source\chap9\mpc.v
source\chap9\mpc_tp.v
source\chap9\mux_case.v
source\chap9\mux_if.v
source\chap9\parity.v
source\chap9\ram256x8.v
source\chap9\reg8.v
source\chap9\rom.v
source\chap9\serial_pal.v
source\chap9\shifter.v
source\chap9\tri_1.v
source\chap9\tri_2.v
source\chap9\updown_count.v
examples.pdf
source\chap10
source\chap11
source\chap12
source\chap3
source\chap5
source\chap6
source\chap7
source\chap8
source\chap9
source
Verilog HDL程序设计教程.pdf