文件名称:MIIPS CPU VHDL源代码
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- 上传时间:2010-11-22
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文件大小:92.73kb
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该文件是一个较简单的MIIPS CPU的Verilog 源代码
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压缩包 : processor.rar 列表 processor\mips.v processor\mux3.v.bak processor\mux3.v processor\memfile.dat processor\sl2.v processor\regfile.v processor\signext.v processor\hazardunit.v processor\datapath.v.bak processor\datapath.v processor\testbench.v.bak processor\testbench.v processor\processor.cr.mti processor\memfile.dat.bak processor\processor.mpf processor\transcript processor\datapath1.v processor\hewenjuan.mpf processor\test_flop.v processor\flop.v processor\equal.v processor\flopr.v processor\top.v processor\adder.v processor\mux2.v processor\controller.v processor\dmem.v processor\vsim.wlf processor\alu.v processor\imem.v processor\hewenjuan.cr.mti processor\top.v.bak processor\flopr1.v processor\flopr3.v processor\flopr4.v processor\flop2.v processor\controller.v.bak processor\mips.v.bak processor\work\_info processor\work\memfile.dat processor\work\flopr11\_primary.vhd processor\work\flopr11\verilog.asm processor\work\flopr11\_primary.dat processor\work\flopr11 processor\work\mux4\_primary.vhd processor\work\mux4\verilog.asm processor\work\mux4\_primary.dat processor\work\mux4 processor\work\hazardunit\_primary.vhd processor\work\hazardunit\verilog.asm processor\work\hazardunit\_primary.dat processor\work\hazardunit processor\work\regfile\_primary.vhd processor\work\regfile\verilog.asm processor\work\regfile\_primary.dat processor\work\regfile processor\work\signext\_primary.vhd processor\work\signext\verilog.asm processor\work\signext\_primary.dat processor\work\signext processor\work\sl2\_primary.vhd processor\work\sl2\verilog.asm processor\work\sl2\_primary.dat processor\work\sl2 processor\work\flopr4\_primary.vhd processor\work\flopr4\verilog.asm processor\work\flopr4\_primary.dat processor\work\flopr4 processor\work\flopr3\_primary.vhd processor\work\flopr3\verilog.asm processor\work\flopr3\_primary.dat processor\work\flopr3 processor\work\flopr2\_primary.vhd processor\work\flopr2\verilog.asm processor\work\flopr2\_primary.dat processor\work\flopr2 processor\work\flopr1\_primary.vhd processor\work\flopr1\verilog.asm processor\work\flopr1\_primary.dat processor\work\flopr1 processor\work\aludec\_primary.vhd processor\work\aludec\verilog.asm processor\work\aludec\_primary.dat processor\work\aludec processor\work\maindec\_primary.vhd processor\work\maindec\verilog.asm processor\work\maindec\_primary.dat processor\work\maindec processor\work\controller\_primary.vhd processor\work\controller\verilog.asm processor\work\controller\_primary.dat processor\work\controller processor\work\datapath\_primary.vhd processor\work\datapath\verilog.asm processor\work\datapath\_primary.dat processor\work\datapath processor\work\flopr\_primary.vhd processor\work\flopr\verilog.asm processor\work\flopr\_primary.dat processor\work\flopr processor\work\mux3\_primary.vhd processor\work\mux3\verilog.asm processor\work\mux3\_primary.dat processor\work\mux3 processor\work\mux2\_primary.vhd processor\work\mux2\verilog.asm processor\work\mux2\_primary.dat processor\work\mux2 processor\work\adder\_primary.vhd processor\work\adder\verilog.asm processor\work\adder\_primary.dat processor\work\adder processor\work\alu\_primary.vhd processor\work\alu\verilog.asm processor\work\alu\_primary.dat processor\work\alu processor\work\equal\_primary.vhd processor\work\equal\verilog.asm processor\work\equal\_primary.dat processor\work\equal processor\work\dmem\_primary.vhd processor\work\dmem\verilog.asm processor\work\dmem\_primary.dat processor\work\dmem processor\work\imem\_primary.vhd processor\work\imem\verilog.asm processor\work\imem\_primary.dat processor\work\imem processor\work\mips\_primary.vhd processor\work\mips\verilog.asm processor\work\mips\_primary.dat processor\work\mips processor\work\top\_primary.vhd processor\work\top\verilog.asm processor\work\top\_primary.dat processor\work\top processor\work\testbench\_primary.vhd processor\work\testbench\verilog.asm processor\work\testbench\_primary.dat processor\work\testbench processor\work processor
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