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文件名称:直流电机的verilog hdl 代码

  • 所属分类：
    VHDL编程
  • 标签属性：
    [VHDL] [源码]
  • 上传时间：
    2012-08-27
  • 文件大小：
    4.8mb
  • 已下载：
    0次
  • 提 供 者：
    黄***
  • 相关连接：
    无
  • 下载说明：
    别用迅雷下载，失败请重下，重下不扣分！
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直流电机的verilog hdl 代码，适合初学者参考,DC motor verilog hdl code, suitable for beginners reference
(系统自动生成,下载前可以参看下载内容)

下载文件列表

Core_PWM Verilog语言编写(可用于电机驱动)/PWM/Project/PWM/assert.log
Core_PWM Verilog语言编写(可用于电机驱动)/PWM/Project/PWM/constraint/pwm_top.pdc
Core_PWM Verilog语言编写(可用于电机驱动)/PWM/Project/PWM/constraint/top_sdc.sdc
Core_PWM Verilog语言编写(可用于电机驱动)/PWM/Project/PWM/designer/impl1/control.adb
Core_PWM Verilog语言编写(可用于电机驱动)/PWM/Project/PWM/designer/impl1/control.ide_des
Core_PWM Verilog语言编写(可用于电机驱动)/PWM/Project/PWM/designer/impl1/control.tcl
Core_PWM Verilog语言编写(可用于电机驱动)/PWM/Project/PWM/designer/impl1/designer.log
Core_PWM Verilog语言编写(可用于电机驱动)/PWM/Project/PWM/designer/impl1/designer_genhdl.log
Core_PWM Verilog语言编写(可用于电机驱动)/PWM/Project/PWM/designer/impl1/designer_gen_ba.log
Core_PWM Verilog语言编写(可用于电机驱动)/PWM/Project/PWM/designer/impl1/simulation/postlayout/stimulus/verilog.psm
Core_PWM Verilog语言编写(可用于电机驱动)/PWM/Project/PWM/designer/impl1/simulation/postlayout/stimulus/_primary.dat
Core_PWM Verilog语言编写(可用于电机驱动)/PWM/Project/PWM/designer/impl1/simulation/postlayout/stimulus/_primary.vhd
Core_PWM Verilog语言编写(可用于电机驱动)/PWM/Project/PWM/designer/impl1/simulation/postlayout/tb_clock_minmax/verilog.psm
Core_PWM Verilog语言编写(可用于电机驱动)/PWM/Project/PWM/designer/impl1/simulation/postlayout/tb_clock_minmax/_primary.dat
Core_PWM Verilog语言编写(可用于电机驱动)/PWM/Project/PWM/designer/impl1/simulation/postlayout/tb_clock_minmax/_primary.vhd
Core_PWM Verilog语言编写(可用于电机驱动)/PWM/Project/PWM/designer/impl1/simulation/postlayout/testbench/verilog.psm
Core_PWM Verilog语言编写(可用于电机驱动)/PWM/Project/PWM/designer/impl1/simulation/postlayout/testbench/_primary.dat
Core_PWM Verilog语言编写(可用于电机驱动)/PWM/Project/PWM/designer/impl1/simulation/postlayout/testbench/_primary.vhd
Core_PWM Verilog语言编写(可用于电机驱动)/PWM/Project/PWM/designer/impl1/simulation/postlayout/top/verilog.psm
Core_PWM Verilog语言编写(可用于电机驱动)/PWM/Project/PWM/designer/impl1/simulation/postlayout/top/_primary.dat
Core_PWM Verilog语言编写(可用于电机驱动)/PWM/Project/PWM/designer/impl1/simulation/postlayout/top/_primary.vhd
Core_PWM Verilog语言编写(可用于电机驱动)/PWM/Project/PWM/designer/impl1/simulation/postlayout/_info
Core_PWM Verilog语言编写(可用于电机驱动)/PWM/Project/PWM/designer/impl1/top.adb
Core_PWM Verilog语言编写(可用于电机驱动)/PWM/Project/PWM/designer/impl1/top.dtf/verify.log
Core_PWM Verilog语言编写(可用于电机驱动)/PWM/Project/PWM/designer/impl1/top.ide_des
Core_PWM Verilog语言编写(可用于电机驱动)/PWM/Project/PWM/designer/impl1/top.pdb
Core_PWM Verilog语言编写(可用于电机驱动)/PWM/Project/PWM/designer/impl1/top.pdb.depends
Core_PWM Verilog语言编写(可用于电机驱动)/PWM/Project/PWM/designer/impl1/top.tcl
Core_PWM Verilog语言编写(可用于电机驱动)/PWM/Project/PWM/designer/impl1/top_ba.sdf
Core_PWM Verilog语言编写(可用于电机驱动)/PWM/Project/PWM/designer/impl1/top_ba.v
Core_PWM Verilog语言编写(可用于电机驱动)/PWM/Project/PWM/hdl/hdlsynchk.tcl
Core_PWM Verilog语言编写(可用于电机驱动)/PWM/Project/PWM/hdl/PWM.v
Core_PWM Verilog语言编写(可用于电机驱动)/PWM/Project/PWM/hdl/PWM_contr.v
Core_PWM Verilog语言编写(可用于电机驱动)/PWM/Project/PWM/hdl/TOP.v
Core_PWM Verilog语言编写(可用于电机驱动)/PWM/Project/PWM/PWM.prj
Core_PWM Verilog语言编写(可用于电机驱动)/PWM/Project/PWM/simulation/meminit.dat
Core_PWM Verilog语言编写(可用于电机驱动)/PWM/Project/PWM/simulation/modelsim.ini
Core_PWM Verilog语言编写(可用于电机驱动)/PWM/Project/PWM/simulation/modelsim.ini.sav
Core_PWM Verilog语言编写(可用于电机驱动)/PWM/Project/PWM/simulation/modelsim.log
Core_PWM Verilog语言编写(可用于电机驱动)/PWM/Project/PWM/simulation/postsynth/@p@l@l_1/verilog.psm
Core_PWM Verilog语言编写(可用于电机驱动)/PWM/Project/PWM/simulation/postsynth/@p@l@l_1/_primary.dat
Core_PWM Verilog语言编写(可用于电机驱动)/PWM/Project/PWM/simulation/postsynth/@p@l@l_1/_primary.vhd
Core_PWM Verilog语言编写(可用于电机驱动)/PWM/Project/PWM/simulation/postsynth/@p@w@m/verilog.psm
Core_PWM Verilog语言编写(可用于电机驱动)/PWM/Project/PWM/simulation/postsynth/@p@w@m/_primary.dat
Core_PWM Verilog语言编写(可用于电机驱动)/PWM/Project/PWM/simulation/postsynth/@p@w@m/_primary.vhd
Core_PWM Verilog语言编写(可用于电机驱动)/PWM/Project/PWM/simulation/postsynth/control/verilog.psm
Core_PWM Verilog语言编写(可用于电机驱动)/PWM/Project/PWM/simulation/postsynth/control/_primary.dat
Core_PWM Verilog语言编写(可用于电机驱动)/PWM/Project/PWM/simulation/postsynth/control/_primary.vhd
Core_PWM Verilog语言编写(可用于电机驱动)/PWM/Project/PWM/simulation/postsynth/stimulus/verilog.psm
Core_PWM Verilog语言编写(可用于电机驱动)/PWM/Project/PWM/simulation/postsynth/stimulus/_primary.dat
Core_PWM Verilog语言编写(可用于电机驱动)/PWM/Project/PWM/simulation/postsynth/stimulus/_primary.vhd
Core_PWM Verilog语言编写(可用于电机驱动)/PWM/Project/PWM/simulation/postsynth/tb_clock_minmax/verilog.psm
Core_PWM Verilog语言编写(可用于电机驱动)/PWM/Project/PWM/simulation/postsynth/tb_clock_minmax/_primary.dat
Core_PWM Verilog语言编写(可用于电机驱动)/PWM/Project/PWM/simulation/postsynth/tb_clock_minmax/_primary.vhd
Core_PWM Verilog语言编写(可用于电机驱动)/PWM/Project/PWM/simulation/postsynth/testbench/verilog.psm
Core_PWM Verilog语言编写(可用于电机驱动)/PWM/Project/PWM/simulation/postsynth/testbench/_primary.dat
Core_PWM Verilog语言编写(可用于电机驱动)/PWM/Project/PWM/simulation/postsynth/testbench/_primary.vhd
Core_PWM Verilog语言编写(可用于电机驱动)/PWM/Project/PWM/simulation/postsynth/top/verilog.psm
Core_PWM Verilog语言编写(可用于电机驱动)/PWM/Project/PWM/simulation/postsynth/top/_primary.dat
Core_PWM Verilog语言编写(可用于电机驱动)/PWM/Project/PWM/simulation/postsynth/top/_primary.vhd
Core_PWM Verilog语言编写(可用于电机驱动)/PWM/Project/PWM/simulation/postsynth/_info
Core_PWM Verilog语言编写(可用

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