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文件名称:开源软核处理器OpenRisc的SOPC设计

  • 所属分类：
    VHDL编程
  • 标签属性：
    [ASM] [源码]
  • 上传时间：
    2012-08-27
  • 文件大小：
    764.96kb
  • 已下载：
    1次
  • 提 供 者：
    邓****
  • 相关连接：
    无
  • 下载说明：
    别用迅雷下载，失败请重下，重下不扣分！
修正介绍说明

介绍说明－－下载内容来自于网络，使用问题请自行百度

开源软核处理器OpenRisc的SOPC设计,开源软核处理器OpenRisc的SOPC设计
相关搜索： openrisc 软核

(系统自动生成,下载前可以参看下载内容)

下载文件列表

or1200-1.35/bench/verilog/or1200_top_bench.v
or1200-1.35/bench/verilog/timescale.v
or1200-1.35/rtl/verilog/or1200_alu.v
or1200-1.35/rtl/verilog/or1200_amultp2_32x32.v
or1200-1.35/rtl/verilog/or1200_cfgr.v
or1200-1.35/rtl/verilog/or1200_cpu.v
or1200-1.35/rtl/verilog/or1200_ctrl.v
or1200-1.35/rtl/verilog/or1200_dc_fsm.v
or1200-1.35/rtl/verilog/or1200_dc_ram.v
or1200-1.35/rtl/verilog/or1200_dc_tag.v
or1200-1.35/rtl/verilog/or1200_dc_top.v
or1200-1.35/rtl/verilog/or1200_defines.v
or1200-1.35/rtl/verilog/or1200_dmmu_tlb.v
or1200-1.35/rtl/verilog/or1200_dmmu_top.v
or1200-1.35/rtl/verilog/or1200_dpram_32x32.v
or1200-1.35/rtl/verilog/or1200_du.v
or1200-1.35/rtl/verilog/or1200_except.v
or1200-1.35/rtl/verilog/or1200_freeze.v
or1200-1.35/rtl/verilog/or1200_genpc.v
or1200-1.35/rtl/verilog/or1200_gmultp2_32x32.v
or1200-1.35/rtl/verilog/or1200_ic_fsm.v
or1200-1.35/rtl/verilog/or1200_ic_ram.v
or1200-1.35/rtl/verilog/or1200_ic_tag.v
or1200-1.35/rtl/verilog/or1200_ic_top.v
or1200-1.35/rtl/verilog/or1200_if.v
or1200-1.35/rtl/verilog/or1200_immu_tlb.v
or1200-1.35/rtl/verilog/or1200_immu_top.v
or1200-1.35/rtl/verilog/or1200_lsu.v
or1200-1.35/rtl/verilog/or1200_mem2reg.v
or1200-1.35/rtl/verilog/or1200_mult_mac.v
or1200-1.35/rtl/verilog/or1200_operandmuxes.v
or1200-1.35/rtl/verilog/or1200_pic.v
or1200-1.35/rtl/verilog/or1200_pm.v
or1200-1.35/rtl/verilog/or1200_reg2mem.v
or1200-1.35/rtl/verilog/or1200_rf.v
or1200-1.35/rtl/verilog/or1200_rfram_generic.v
or1200-1.35/rtl/verilog/or1200_sb.v
or1200-1.35/rtl/verilog/or1200_sb_fifo.v
or1200-1.35/rtl/verilog/or1200_spram_1024x32.v
or1200-1.35/rtl/verilog/or1200_spram_1024x8.v
or1200-1.35/rtl/verilog/or1200_spram_2048x32.v
or1200-1.35/rtl/verilog/or1200_spram_2048x8.v
or1200-1.35/rtl/verilog/or1200_spram_256x21.v
or1200-1.35/rtl/verilog/or1200_spram_512x20.v
or1200-1.35/rtl/verilog/or1200_spram_64x14.v
or1200-1.35/rtl/verilog/or1200_spram_64x22.v
or1200-1.35/rtl/verilog/or1200_spram_64x24.v
or1200-1.35/rtl/verilog/or1200_sprs.v
or1200-1.35/rtl/verilog/or1200_top.v
or1200-1.35/rtl/verilog/or1200_tpram_32x32.v
or1200-1.35/rtl/verilog/or1200_tt.v
or1200-1.35/rtl/verilog/or1200_wbmux.v
or1200-1.35/rtl/verilog/or1200_wb_biu.v
or1200-1.35/rtl/verilog/or1200_xcv_ram32x8d.v
or1200-1.35/rtl/verilog/timescale.v
or1200-1.35/sim/rtl_sim/modelsim_sim/modelsim.ini
or1200-1.35/sim/rtl_sim/modelsim_sim/or1200.cr.mti
or1200-1.35/sim/rtl_sim/modelsim_sim/or1200.mpf
or1200-1.35/sim/rtl_sim/modelsim_sim/run.do
or1200-1.35/sim/rtl_sim/modelsim_sim/transcript
or1200-1.35/sim/rtl_sim/modelsim_sim/vlog.opt
or1200-1.35/sim/rtl_sim/modelsim_sim/vsim.wlf
or1200-1.35/sim/rtl_sim/modelsim_sim/wave.do
or1200-1.35/sim/rtl_sim/modelsim_sim/work/or1200_alu/verilog.asm
or1200-1.35/sim/rtl_sim/modelsim_sim/work/or1200_alu/_primary.dat
or1200-1.35/sim/rtl_sim/modelsim_sim/work/or1200_alu/_primary.vhd
or1200-1.35/sim/rtl_sim/modelsim_sim/work/or1200_cfgr/verilog.asm
or1200-1.35/sim/rtl_sim/modelsim_sim/work/or1200_cfgr/_primary.dat
or1200-1.35/sim/rtl_sim/modelsim_sim/work/or1200_cfgr/_primary.vhd
or1200-1.35/sim/rtl_sim/modelsim_sim/work/or1200_cpu/verilog.asm
or1200-1.35/sim/rtl_sim/modelsim_sim/work/or1200_cpu/_primary.dat
or1200-1.35/sim/rtl_sim/modelsim_sim/work/or1200_cpu/_primary.vhd
or1200-1.35/sim/rtl_sim/modelsim_sim/work/or1200_ctrl/verilog.asm
or1200-1.35/sim/rtl_sim/modelsim_sim/work/or1200_ctrl/_primary.dat
or1200-1.35/sim/rtl_sim/modelsim_sim/work/or1200_ctrl/_primary.vhd
or1200-1.35/sim/rtl_sim/modelsim_sim/work/or1200_dc_fsm/verilog.asm
or1200-1.35/sim/rtl_sim/modelsim_sim/work/or1200_dc_fsm/_primary.dat
or1200-1.35/sim/rtl_sim/modelsim_sim/work/or1200_dc_fsm/_primary.vhd
or1200-1.35/sim/rtl_sim/modelsim_sim/work/or1200_dc_ram/verilog.asm
or1200-1.35/sim/rtl_sim/modelsim_sim/work/or1200_dc_ram/_primary.dat
or1200-1.35/sim/rtl_sim/modelsim_sim/work/or1200_dc_ram/_primary.vhd
or1200-1.35/sim/rtl_sim/modelsim_sim/work/or1200_dc_tag/verilog.asm
or1200-1.35/sim/rtl_sim/modelsim_sim/work/or1200_dc_tag/_primary.dat
or1200-1.35/sim/rtl_sim/modelsim_sim/work/or1200_dc_tag/_primary.vhd
or1200-1.35/sim/rtl_sim/modelsim_sim/work/or1200_dc_top/verilog.asm
or1200-1.35/sim/rtl_sim/modelsim_sim/work/or1200_dc_top/_primary.dat
or1200-1.35/sim/rtl_sim/modelsim_sim/work/or1200_dc_top/_primary.vhd
or1200-1.35/sim/rtl_sim/modelsim_sim/work/or1200_dmmu_tlb/verilog.asm
or1200-1.35/sim/rtl_sim/modelsim_sim/work/or1200_dmmu_tlb/_primary.dat
or1200-1.35/sim/rtl_sim/modelsim_sim/work/or1200_dmmu_tlb/_primary.vhd
or1200-1.35/sim/rtl_sim/modelsim_sim/work/or1200_dmmu_top/verilog.asm
or1200-1.35/sim/rtl_sim/modelsim_sim/work/or1200_dmmu_top/_primary.dat
or1200-1.35/sim/rtl_sim/modelsim_sim/work/or1200_dmmu_top/_primary.vhd
or1200-1.35/sim/rtl_sim/modelsim_sim/work/or1200_dpram_32x32/verilog.asm
or1200-1.35/sim/rtl_sim/modelsim_sim/work/or1200_dpram_32x32/_primary.dat
or1200-1.35/sim/rtl_sim/modelsim_sim/work/or1200_dpram_32x32/_primary.vhd
or1200-1.35/sim/rtl_sim/modelsim_sim/work/or1200_du/verilog.asm
or1200-1.35/sim/rtl_sim/modelsim_sim/work/or1200_du/_primary.dat
or1200-1.35/sim/rtl_sim/modelsim_sim/work/or1200_du/_primary.vhd
or1200-1.35/sim/rtl_sim

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