文件名称:Verilog数字系统设计教程(第2版)
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Verilog数字系统设计教程(第2版)”这本书的思考题没有答案，要多做实验和仿真-• Source code of designs in chapters 1 to 8.
• Chapter 8 designs include the SAYEH processor, its C Compiler, and its Sort program run files.
• Several Designs, including SAYEH, that are programmed on Altera’s UP2 board are included in “Quartus UP2 Designs.zip”
• The OVL directory has OVL library version 1.0 and its documentations
• In the Software directory, the Altera directory contains Quartus II, related tools, and Altera device specifications. Please connect to www.altera.com and then click on “University Program” to obtain a license for Quartus II Web Edition.
• In the Software directory, The MentorGraphics directory has the ModelSim-Altera simulation program. Please connect to www.altera.com and then click on “University Program” to obtain a license for ModelSim-Altera.
• Chapter 8 designs include the SAYEH processor, its C Compiler, and its Sort program run files.
• Several Designs, including SAYEH, that are programmed on Altera’s UP2 board are included in “Quartus UP2 Designs.zip”
• The OVL directory has OVL library version 1.0 and its documentations
• In the Software directory, the Altera directory contains Quartus II, related tools, and Altera device specifications. Please connect to www.altera.com and then click on “University Program” to obtain a license for Quartus II Web Edition.
• In the Software directory, The MentorGraphics directory has the ModelSim-Altera simulation program. Please connect to www.altera.com and then click on “University Program” to obtain a license for ModelSim-Altera.
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下载文件列表
Chapter 1/chap1counter.v
Chapter 1/Chap1CounterTester.v
Chapter 1/confn.v
Chapter 1/dlatch.v
Chapter 1/dreg.v
Chapter 1/latchtest.v
Chapter 1/parity.v
Chapter 1/srlatch.v
Chapter 1
Chapter 1/Chap1CounterTester.v
Chapter 1/confn.v
Chapter 1/dlatch.v
Chapter 1/dreg.v
Chapter 1/latchtest.v
Chapter 1/parity.v
Chapter 1/srlatch.v
Chapter 1
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